From aad9bad32604645e2d61f0858234a1838e8b88eb Mon Sep 17 00:00:00 2001
From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Tue, 27 Aug 2019 13:56:26 +0300
Subject: [PATCH] Add tests for macc and rom;

Test cases from
https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071;
In both cases synthesized only LUTs and DFFs.
---
 tests/ice40/macc.v  | 22 ++++++++++++++++++++++
 tests/ice40/macc.ys | 10 ++++++++++
 tests/ice40/rom.v   | 15 +++++++++++++++
 tests/ice40/rom.ys  |  8 ++++++++
 4 files changed, 55 insertions(+)
 create mode 100644 tests/ice40/macc.v
 create mode 100644 tests/ice40/macc.ys
 create mode 100644 tests/ice40/rom.v
 create mode 100644 tests/ice40/rom.ys

diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v
new file mode 100644
index 000000000..115f8ce42
--- /dev/null
+++ b/tests/ice40/macc.v
@@ -0,0 +1,22 @@
+module top(clk,a,b,c,set);
+parameter A_WIDTH = 4;
+parameter B_WIDTH = 3;
+input set;
+input clk;
+input signed [(A_WIDTH - 1):0] a;
+input signed [(B_WIDTH - 1):0] b;
+output signed [(A_WIDTH + B_WIDTH - 1):0] c;
+reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
+assign c = reg_tmp_c;
+always @(posedge clk)
+begin
+if(set)
+begin
+reg_tmp_c <= 0;
+end
+else
+begin
+reg_tmp_c <= a * b + c;
+end
+end
+endmodule
diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys
new file mode 100644
index 000000000..233e7e890
--- /dev/null
+++ b/tests/ice40/macc.ys
@@ -0,0 +1,10 @@
+read_verilog macc.v
+proc
+hierarchy -top top
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 41 t:SB_LUT4
+select -assert-count 6 t:SB_CARRY
+select -assert-count 7 t:SB_DFFSR
+select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D
diff --git a/tests/ice40/rom.v b/tests/ice40/rom.v
new file mode 100644
index 000000000..c31ca3b2b
--- /dev/null
+++ b/tests/ice40/rom.v
@@ -0,0 +1,15 @@
+module top(data, addr);
+output [3:0] data;
+input [4:0] addr;
+always @(addr) begin
+case (addr)
+0 : data = 'h4;
+1 : data = 'h9;
+2 : data = 'h1;
+15 : data = 'h8;
+16 : data = 'h1;
+17 : data = 'h0;
+default : data = 'h0;
+endcase
+end
+endmodule
diff --git a/tests/ice40/rom.ys b/tests/ice40/rom.ys
new file mode 100644
index 000000000..41d214e2a
--- /dev/null
+++ b/tests/ice40/rom.ys
@@ -0,0 +1,8 @@
+read_verilog rom.v
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 5 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D