mirror of https://github.com/YosysHQ/yosys.git
Fixes for reverting SigSpec helper functions
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@ -155,9 +155,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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// If we have a signed multiply-add, then perform sign extension
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// TODO: Need to check CD[31:16] is sign extension of CD[15:0]?
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if (st.addAB->getParam("\\A_SIGNED").as_bool() && st.addAB->getParam("\\B_SIGNED").as_bool())
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pm.module->connect(O[-1], O[-2]);
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pm.module->connect(O[32], O[31]);
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else
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cell->setPort("\\CO", O[-1]);
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cell->setPort("\\CO", O[32]);
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O.remove(O_width-1);
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}
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else
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@ -206,10 +206,12 @@ match ffO_lo
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endmatch
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code
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if (ffO_lo) {
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SigSpec O = sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()));
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O.remove_const();
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if (!includes(port(ffO_lo, \D).to_sigbit_set(), O.to_sigbit_set()))
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reject;
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}
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endcode
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match ffO_hi
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@ -220,10 +222,12 @@ match ffO_hi
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endmatch
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code
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if (ffO_hi) {
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SigSpec O = sigOused.extract_end(16);
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O.remove_const();
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if (!includes(port(ffO_hi, \D).to_sigbit_set(), O.to_sigbit_set()))
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reject;
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}
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endcode
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code clock clock_pol sigO sigCD
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