opt_clean: add init test

This commit is contained in:
Eddie Hung 2020-05-14 00:26:23 -07:00
parent fc9fb09a91
commit aa4a69f89b
1 changed files with 13 additions and 0 deletions

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@ -0,0 +1,13 @@
logger -expect warning "Initial value conflict for wire '\\y' and value '1'0'" 1
logger -expect-no-warnings
read_verilog <<EOT
module top;
(* init=1'b0 *) wire w = 1'b0;
(* init=1'bx *) wire x = 1'b0;
(* init=1'b1 *) wire y = 1'b0;
(* init=1'b0 *) wire z = 1'bx;
endmodule
EOT
clean
select -assert-count 1 a:init
select -assert-count 1 w:y a:init %i