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opt_clean: add init test
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logger -expect warning "Initial value conflict for wire '\\y' and value '1'0'" 1
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logger -expect-no-warnings
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read_verilog <<EOT
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module top;
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(* init=1'b0 *) wire w = 1'b0;
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(* init=1'bx *) wire x = 1'b0;
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(* init=1'b1 *) wire y = 1'b0;
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(* init=1'b0 *) wire z = 1'bx;
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endmodule
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EOT
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clean
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select -assert-count 1 a:init
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select -assert-count 1 w:y a:init %i
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