mirror of https://github.com/YosysHQ/yosys.git
Support CEA
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09c26c55bb
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@ -32,6 +32,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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#if 1
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#if 1
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log("\n");
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log("\n");
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log("ffA: %s\n", log_id(st.ffA, "--"));
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log("ffA: %s\n", log_id(st.ffA, "--"));
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log("ffAmux: %s\n", log_id(st.ffAmux, "--"));
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log("ffB: %s\n", log_id(st.ffB, "--"));
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log("ffB: %s\n", log_id(st.ffB, "--"));
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log("dsp: %s\n", log_id(st.dsp, "--"));
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log("dsp: %s\n", log_id(st.dsp, "--"));
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log("ffM: %s\n", log_id(st.ffM, "--"));
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log("ffM: %s\n", log_id(st.ffM, "--"));
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@ -78,15 +79,19 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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if (st.ffA) {
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if (st.ffA) {
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SigSpec A = cell->getPort("\\A");
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SigSpec A = cell->getPort("\\A");
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SigSpec D = st.ffA->getPort("\\D");
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SigSpec D = st.ffA->getPort("\\D");
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SigSpec Q = st.ffA->getPort("\\Q");
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SigSpec Q = pm.sigmap(st.ffA->getPort("\\Q"));
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A.replace(Q, D);
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A.replace(Q, D);
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cell->setPort("\\A", A);
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cell->setParam("\\AREG", 1);
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cell->setParam("\\AREG", 1);
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if (st.ffA->type == "$dff")
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if (st.ffAmux) {
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SigSpec Y = st.ffAmux->getPort("\\Y");
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SigSpec AB = st.ffAmux->getPort(st.ffAmuxAB == "\\A" ? "\\B" : "\\A");
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A.replace(Y, AB);
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cell->setPort("\\CEA2", st.ffAmux->getPort("\\S"));
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}
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else
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cell->setPort("\\CEA2", State::S1);
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cell->setPort("\\CEA2", State::S1);
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//else if (st.ffA->type == "$dffe")
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cell->setPort("\\A", A);
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// cell->setPort("\\CEA2", st.ffA->getPort("\\EN"));
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else log_abort();
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}
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}
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if (st.ffB) {
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if (st.ffB) {
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SigSpec B = cell->getPort("\\B");
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SigSpec B = cell->getPort("\\B");
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@ -1,8 +1,8 @@
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pattern xilinx_dsp
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pattern xilinx_dsp
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state <SigBit> clock
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state <SigBit> clock
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state <SigSpec> sigA sigB sigC sigM sigP sigPused
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state <SigSpec> sigA sigffAmux sigB sigC sigM sigP sigPused
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state <IdString> ffMmuxAB postAddAB postAddMuxAB
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state <IdString> ffAmuxAB ffMmuxAB postAddAB postAddMuxAB
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match dsp
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match dsp
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select dsp->type.in(\DSP48E1)
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select dsp->type.in(\DSP48E1)
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@ -14,11 +14,17 @@ code sigA sigB
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for (i = GetSize(sigA)-1; i > 0; i--)
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for (i = GetSize(sigA)-1; i > 0; i--)
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if (sigA[i] != sigA[i-1])
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if (sigA[i] != sigA[i-1])
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break;
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break;
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// Do not remove non-const sign bit
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if (sigA[i].wire)
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++i;
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sigA.remove(i, GetSize(sigA)-i);
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sigA.remove(i, GetSize(sigA)-i);
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sigB = port(dsp, \B);
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sigB = port(dsp, \B);
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for (i = GetSize(sigB)-1; i > 0; i--)
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for (i = GetSize(sigB)-1; i > 0; i--)
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if (sigB[i] != sigB[i-1])
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if (sigB[i] != sigB[i-1])
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break;
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break;
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// Do not remove non-const sign bit
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if (sigB[i].wire)
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++i;
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sigB.remove(i, GetSize(sigB)-i);
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sigB.remove(i, GetSize(sigB)-i);
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endcode
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endcode
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@ -43,20 +49,34 @@ match ffA
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select param(ffA, \CLK_POLARITY).as_bool()
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select param(ffA, \CLK_POLARITY).as_bool()
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filter GetSize(port(ffA, \Q)) >= GetSize(sigA)
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filter GetSize(port(ffA, \Q)) >= GetSize(sigA)
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slice offset GetSize(port(ffA, \Q))
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slice offset GetSize(port(ffA, \Q))
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filter offset+GetSize(sigA) <= GetSize(port(ffA, \Q)) && nusers(port(ffA, \Q).extract(offset, GetSize(sigA))) <= 3
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filter offset+GetSize(sigA) <= GetSize(port(ffA, \Q)) && port(ffA, \Q).extract(offset, GetSize(sigA)) == sigA
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filter offset+GetSize(sigA) <= GetSize(port(ffA, \Q)) && port(ffA, \Q).extract(offset, GetSize(sigA)) == sigA
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optional
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optional
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endmatch
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endmatch
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code clock
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code sigA sigffAmux clock
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if (ffA) {
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if (ffA) {
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for (auto b : port(ffA, \Q))
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for (auto b : port(ffA, \Q))
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if (b.wire->get_bool_attribute(\keep))
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if (b.wire->get_bool_attribute(\keep))
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reject;
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reject;
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clock = port(ffA, \CLK).as_bit();
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clock = port(ffA, \CLK).as_bit();
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if (nusers(sigA) == 3)
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sigffAmux = sigA;
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sigA.replace(port(ffA, \Q), port(ffA, \D));
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}
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}
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endcode
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endcode
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match ffAmux
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if sigffAmux != SigSpec()
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select ffAmux->type.in($mux)
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(ffAmux, \Y) === sigA
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index <SigSpec> port(ffAmux, AB) === sigffAmux
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set ffAmuxAB AB
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endmatch
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match ffB
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match ffB
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if param(dsp, \BREG).as_int() == 0
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if param(dsp, \BREG).as_int() == 0
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select ffB->type.in($dff)
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select ffB->type.in($dff)
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