riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

dffinit -noreinit to silently continue when init value is 1'bx

This commit is contained in:
Eddie Hung 2019-05-02 17:40:39 -07:00
parent 98925f6c4b
commit aa081f83c7
1 changed files with 12 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
passes/techmap/dffinit.cc
View File

@ -135,10 +135,18 @@ struct DffinitPass : public Pass {
continue; continue;
while (GetSize(value.bits) <= i) while (GetSize(value.bits) <= i)
value.bits.push_back(State::S0); value.bits.push_back(State::S0);
if (noreinit && value.bits[i] != State::Sx && value.bits[i] != init_bits.at(sig[i])) if (noreinit && value.bits[i] != State::Sx && value.bits[i] != init_bits.at(sig[i])) {
if (init_bits.at(sig[i]) != State::Sx) {
log_error("Trying to assign a different init value for %s.%s.%s which technically " log_error("Trying to assign a different init value for %s.%s.%s which technically "
"have a conflicted init value.\n", "have a conflicted init value.\n",
log_id(module), log_id(cell), log_id(it.second)); log_id(module), log_id(cell), log_id(it.second));
}
else {
// Trying to overwrite an existing INIT value with 1'bx,
// silently ignore?
continue;
}
}
value.bits[i] = init_bits.at(sig[i]); value.bits[i] = init_bits.at(sig[i]);
cleanup_bits.insert(sig[i]); cleanup_bits.insert(sig[i]);
} }