mirror of https://github.com/YosysHQ/yosys.git
Removed RTLIL::SigChunk::compare()
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08e1e25169
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@ -1382,6 +1382,7 @@ bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
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if (wire && other.wire)
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if (wire && other.wire)
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if (wire->name != other.wire->name)
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if (wire->name != other.wire->name)
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return wire->name < other.wire->name;
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return wire->name < other.wire->name;
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if (wire != other.wire)
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if (wire != other.wire)
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return wire < other.wire;
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return wire < other.wire;
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@ -1391,10 +1392,7 @@ bool RTLIL::SigChunk::operator <(const RTLIL::SigChunk &other) const
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if (width != other.width)
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if (width != other.width)
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return width < other.width;
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return width < other.width;
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if (data.bits != other.data.bits)
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return data.bits < other.data.bits;
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return data.bits < other.data.bits;
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return false;
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}
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}
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bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
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bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
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@ -1566,28 +1564,11 @@ RTLIL::SigSpec RTLIL::SigSpec::optimized() const
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return ret;
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return ret;
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}
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}
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bool RTLIL::SigChunk::compare(const RTLIL::SigChunk &a, const RTLIL::SigChunk &b)
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{
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if (a.wire != b.wire) {
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if (a.wire == NULL || b.wire == NULL)
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return a.wire < b.wire;
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else if (a.wire->name != b.wire->name)
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return a.wire->name < b.wire->name;
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else
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return a.wire < b.wire;
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}
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if (a.offset != b.offset)
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return a.offset < b.offset;
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if (a.width != b.width)
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return a.width < b.width;
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return a.data.bits < b.data.bits;
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}
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void RTLIL::SigSpec::sort()
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void RTLIL::SigSpec::sort()
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{
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{
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pack();
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pack();
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expand();
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expand();
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std::sort(chunks_.begin(), chunks_.end(), RTLIL::SigChunk::compare);
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std::sort(chunks_.begin(), chunks_.end());
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optimize();
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optimize();
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}
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}
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@ -1595,11 +1576,11 @@ void RTLIL::SigSpec::sort_and_unify()
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{
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{
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pack();
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pack();
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expand();
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expand();
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std::sort(chunks_.begin(), chunks_.end(), RTLIL::SigChunk::compare);
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std::sort(chunks_.begin(), chunks_.end());
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for (size_t i = 1; i < chunks_.size(); i++) {
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for (size_t i = 1; i < chunks_.size(); i++) {
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RTLIL::SigChunk &ch1 = chunks_[i-1];
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RTLIL::SigChunk &ch1 = chunks_[i-1];
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RTLIL::SigChunk &ch2 = chunks_[i];
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RTLIL::SigChunk &ch2 = chunks_[i];
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if (!RTLIL::SigChunk::compare(ch1, ch2) && !RTLIL::SigChunk::compare(ch2, ch1)) {
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if (ch1 == ch2) {
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chunks_.erase(chunks_.begin()+i);
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chunks_.erase(chunks_.begin()+i);
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width_ -= chunks_[i].width;
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width_ -= chunks_[i].width;
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i--;
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i--;
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@ -470,7 +470,6 @@ struct RTLIL::SigChunk {
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bool operator <(const RTLIL::SigChunk &other) const;
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bool operator <(const RTLIL::SigChunk &other) const;
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bool operator ==(const RTLIL::SigChunk &other) const;
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bool operator ==(const RTLIL::SigChunk &other) const;
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bool operator !=(const RTLIL::SigChunk &other) const;
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bool operator !=(const RTLIL::SigChunk &other) const;
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static bool compare(const RTLIL::SigChunk &a, const RTLIL::SigChunk &b);
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};
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};
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struct RTLIL::SigBit {
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struct RTLIL::SigBit {
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