mirror of https://github.com/YosysHQ/yosys.git
abstract: better present changes done
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@ -240,23 +240,20 @@ struct AbstractPass : public Pass {
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Wire *enable_wire = mod->wire("\\" + enable_name);
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if (!enable_wire)
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log_cmd_error("Enable wire %s not found in module %s\n", enable_name.c_str(), mod->name.c_str());
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if (mode == State) {
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// for (auto cell : mod->selected_cells())
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// if (ct.cell_types.count(cell->type))
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if (mode == State)
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changed += abstract_state(mod, {enable_wire, enable_pol});
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} else {
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else
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changed += abstract_value(mod, {enable_wire, enable_pol});
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}
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}
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if (mode == State)
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log("Abstracted %d cells.\n", changed);
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log("Abstracted %d stateful cells.\n", changed);
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else
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log("Abstracted %d values.\n", changed);
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log("Abstracted %d driver ports.\n", changed);
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} else if (mode == Initial) {
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for (auto mod : design->selected_modules()) {
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changed += abstract_init(mod);
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}
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log("Abstracted %d bits.\n", changed);
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log("Abstracted %d init bits.\n", changed);
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} else {
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log_cmd_error("No mode selected, see help message\n");
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}
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