Add some more comments

This commit is contained in:
Eddie Hung 2019-06-10 10:27:55 -07:00
parent 498c21e735
commit a91ea6612a
1 changed files with 6 additions and 1 deletions

View File

@ -2,9 +2,14 @@
set -e
# NB: *.aag and *.aig must contain a symbol table naming the primary
# inputs and outputs, otherwise ABC and Yosys will name them
# arbitrarily (and inconsistently with each other).
for aag in *.aag; do
# Since ABC cannot read *.aag, read the *.aig instead
# (which would have been created by the reference aig2aig utility)
# (which would have been created by the reference aig2aig utility,
# available from http://fmv.jku.at/aiger/)
../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
../../yosys -p "
read_verilog ${aag%.*}_ref.v