riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

backends/firrtl: Ensure `modInstance` is valid 

This should fix #3648 where when calling `emit_elaborated_extmodules` it
checks to see if a module is a black-box, however there was no
validation that the cell type was actually known, and it just always
assumed that we would get a valid instance, causing a segfault.
This commit is contained in:
Aki Van Ness 2023-02-01 10:15:20 -05:00 committed by Aki
parent 221036c5b6
commit a90f940615
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
backends/firrtl/firrtl.cc
View File

@ -346,6 +346,12 @@ void emit_elaborated_extmodules(RTLIL::Design *design, std::ostream &f)
{ {
// Find the module corresponding to this instance. // Find the module corresponding to this instance.
auto modInstance = design->module(cell->type); auto modInstance = design->module(cell->type);
// Ensure that we actually have a module instance
if (modInstance == nullptr) {
log_error("Unknown cell type %s\n", cell->type.c_str());
return;
}
bool modIsBlackbox = modInstance->get_blackbox_attribute(); bool modIsBlackbox = modInstance->get_blackbox_attribute();
if (modIsBlackbox) if (modIsBlackbox)