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Merge pull request #1041 from YosysHQ/clifford/fix1040 

Fix handling of offset and upto module ports in write_blif
This commit is contained in:
Clifford Wolf 2019-05-25 19:17:05 +02:00 committed by GitHub
parent b7dd7c2dcd 6352df42ae
commit a90eec12c9
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 20 additions and 6 deletions
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26
backends/blif/blif.cc
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@ -409,12 +409,26 @@ struct BlifDumper
f << stringf(".%s %s", subckt_or_gate(cell->type.str()), cstr(cell->type)); f << stringf(".%s %s", subckt_or_gate(cell->type.str()), cstr(cell->type));
for (auto &conn : cell->connections()) for (auto &conn : cell->connections())
for (int i = 0; i < conn.second.size(); i++) { {
if (conn.second.size() == 1) if (conn.second.size() == 1) {
f << stringf(" %s", cstr(conn.first)); f << stringf(" %s=%s", cstr(conn.first), cstr(conn.second[0]));
else continue;
f << stringf(" %s[%d]", cstr(conn.first), i); }
f << stringf("=%s", cstr(conn.second.extract(i, 1)));
Module *m = design->module(cell->type);
Wire *w = m ? m->wire(conn.first) : nullptr;
if (w == nullptr) {
for (int i = 0; i < GetSize(conn.second); i++)
f << stringf(" %s[%d]=%s", cstr(conn.first), i, cstr(conn.second[i]));
} else {
for (int i = 0; i < std::min(GetSize(conn.second), GetSize(w)); i++) {
SigBit sig(w, i);
f << stringf(" %s[%d]=%s", cstr(conn.first), sig.wire->upto ?
sig.wire->start_offset+sig.wire->width-sig.offset-1 :
sig.wire->start_offset+sig.offset, cstr(conn.second[i]));
}
}
} }
f << stringf("\n"); f << stringf("\n");