mirror of https://github.com/YosysHQ/yosys.git
Remove vhdl2verilog
This commit is contained in:
Clifford Wolf
parent
c672c321e3
commit
a8cf431d9c
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OBJS += frontends/vhdl2verilog/vhdl2verilog.o
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <errno.h>
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#include <limits.h>
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#ifndef _WIN32
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# include <unistd.h>
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# include <dirent.h>
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#endif
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YOSYS_NAMESPACE_BEGIN
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struct Vhdl2verilogPass : public Pass {
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Vhdl2verilogPass() : Pass("vhdl2verilog", "importing VHDL designs using vhdl2verilog") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" vhdl2verilog [options] <vhdl-file>..\n");
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log("\n");
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log("This command reads VHDL source files using the 'vhdl2verilog' tool and the\n");
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log("Yosys Verilog frontend.\n");
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log("\n");
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log(" -out <out_file>\n");
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log(" do not import the vhdl2verilog output. instead write it to the\n");
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log(" specified file.\n");
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log("\n");
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log(" -vhdl2verilog_dir <directory>\n");
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log(" do use the specified vhdl2verilog installation. this is the directory\n");
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log(" that contains the setup_env.sh file. when this option is not present,\n");
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log(" it is assumed that vhdl2verilog is in the PATH environment variable.\n");
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log("\n");
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log(" -top <top-entity-name>\n");
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log(" The name of the top entity. This option is mandatory.\n");
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log("\n");
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log("The following options are passed as-is to vhdl2verilog:\n");
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log("\n");
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log(" -arch <architecture_name>\n");
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log(" -unroll_generate\n");
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log(" -nogenericeval\n");
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log(" -nouniquify\n");
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log(" -oldparser\n");
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log(" -suppress <list>\n");
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log(" -quiet\n");
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log(" -nobanner\n");
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log(" -mapfile <file>\n");
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log("\n");
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log("vhdl2verilog can be obtained from:\n");
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log("http://www.edautils.com/vhdl2verilog.html\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header(design, "Executing VHDL2VERILOG (importing VHDL designs using vhdl2verilog).\n");
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log_push();
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std::string out_file, top_entity;
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std::string vhdl2verilog_dir;
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std::string extra_opts;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-out" && argidx+1 < args.size()) {
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out_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_entity = args[++argidx];
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continue;
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}
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if (args[argidx] == "-vhdl2verilog_dir" && argidx+1 < args.size()) {
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vhdl2verilog_dir = args[++argidx];
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continue;
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}
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if ((args[argidx] == "-arch" || args[argidx] == "-suppress" || args[argidx] == "-mapfile") && argidx+1 < args.size()) {
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if (args[argidx] == "-mapfile" && !args[argidx+1].empty() && args[argidx+1][0] != '/') {
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char pwd[PATH_MAX];
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if (!getcwd(pwd, sizeof(pwd))) {
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log_cmd_error("getcwd failed: %s", strerror(errno));
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log_abort();
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}
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args[argidx+1] = pwd + ("/" + args[argidx+1]);
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}
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extra_opts += std::string(" ") + args[argidx];
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extra_opts += std::string(" '") + args[++argidx] + std::string("'");
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continue;
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}
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if (args[argidx] == "-unroll_generate" || args[argidx] == "-nogenericeval" || args[argidx] == "-nouniquify" ||
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args[argidx] == "-oldparser" || args[argidx] == "-quiet" || args[argidx] == "-nobanner") {
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extra_opts += std::string(" ") + args[argidx];
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continue;
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}
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break;
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}
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if (argidx == args.size())
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cmd_error(args, argidx, "Missing filenames.");
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if (args[argidx].substr(0, 1) == "-")
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cmd_error(args, argidx, "Unknown option.");
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if (top_entity.empty())
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log_cmd_error("Missing -top option.\n");
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std::string tempdir_name = make_temp_dir("/tmp/yosys-vhdl2verilog-XXXXXX");
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log("Using temp directory %s.\n", tempdir_name.c_str());
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if (!out_file.empty() && out_file[0] != '/') {
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char pwd[PATH_MAX];
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if (!getcwd(pwd, sizeof(pwd))) {
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log_cmd_error("getcwd failed: %s", strerror(errno));
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log_abort();
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}
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out_file = pwd + ("/" + out_file);
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}
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FILE *f = fopen(stringf("%s/files.list", tempdir_name.c_str()).c_str(), "wt");
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while (argidx < args.size()) {
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std::string file = args[argidx++];
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if (file.empty())
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continue;
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if (file[0] != '/') {
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char pwd[PATH_MAX];
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if (!getcwd(pwd, sizeof(pwd))) {
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log_cmd_error("getcwd failed: %s", strerror(errno));
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log_abort();
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}
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file = pwd + ("/" + file);
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}
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fprintf(f, "%s\n", file.c_str());
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log("Adding '%s' to the file list.\n", file.c_str());
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}
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fclose(f);
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std::string command = "exec 2>&1; ";
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if (!vhdl2verilog_dir.empty())
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command += stringf("cd '%s'; . ./setup_env.sh; ", vhdl2verilog_dir.c_str());
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command += stringf("cd '%s'; vhdl2verilog -out '%s' -filelist files.list -top '%s'%s", tempdir_name.c_str(),
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out_file.empty() ? "vhdl2verilog_output.v" : out_file.c_str(), top_entity.c_str(), extra_opts.c_str());
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log("Running '%s'..\n", command.c_str());
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int ret = run_command(command, [](const std::string &line) { log("%s", line.c_str()); });
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if (ret != 0)
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log_error("Execution of command \"%s\" failed: return code %d.\n", command.c_str(), ret);
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if (out_file.empty()) {
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std::ifstream ff;
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ff.open(stringf("%s/vhdl2verilog_output.v", tempdir_name.c_str()).c_str());
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if (ff.fail())
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log_error("Can't open vhdl2verilog output file `vhdl2verilog_output.v'.\n");
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Frontend::frontend_call(design, &ff, stringf("%s/vhdl2verilog_output.v", tempdir_name.c_str()), "verilog");
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}
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log_header(design, "Removing temp directory `%s':\n", tempdir_name.c_str());
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remove_directory(tempdir_name);
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log_pop();
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}
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} Vhdl2verilogPass;
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YOSYS_NAMESPACE_END
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