riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

opt_lut: add -limit option, for debugging misoptimizations.

This commit is contained in:
whitequark 2018-12-07 16:31:15 +00:00
parent 7d1088afc4
commit a8ab722824
1 changed files with 21 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
passes/opt/opt_lut.cc
View File

@ -93,7 +93,7 @@ struct OptLutWorker
} }
} }
OptLutWorker(dict<IdString, dict<int, IdString>> &dlogic, RTLIL::Module *module) : OptLutWorker(dict<IdString, dict<int, IdString>> &dlogic, RTLIL::Module *module, int limit) :
dlogic(dlogic), module(module), index(module), sigmap(module) dlogic(dlogic), module(module), index(module), sigmap(module)
{ {
log("Discovering LUTs.\n"); log("Discovering LUTs.\n");
@ -192,6 +192,12 @@ struct OptLutWorker
pool<RTLIL::Cell*> worklist = luts; pool<RTLIL::Cell*> worklist = luts;
while (worklist.size()) while (worklist.size())
{ {
if (limit == 0)
{
log("Limit reached.\n");
break;
}
auto lutA = worklist.pop(); auto lutA = worklist.pop();
SigSpec lutA_input = sigmap(lutA->getPort("\\A")); SigSpec lutA_input = sigmap(lutA->getPort("\\A"));
SigSpec lutA_output = sigmap(lutA->getPort("\\Y")[0]); SigSpec lutA_output = sigmap(lutA->getPort("\\Y")[0]);
@ -398,6 +404,8 @@ struct OptLutWorker
worklist.erase(lutR); worklist.erase(lutR);
combined_count++; combined_count++;
if (limit > 0)
limit--;
} }
} }
} }
@ -431,17 +439,22 @@ struct OptLutPass : public Pass {
log(" the case where both LUT and dedicated logic input are connected to\n"); log(" the case where both LUT and dedicated logic input are connected to\n");
log(" the same constant.\n"); log(" the same constant.\n");
log("\n"); log("\n");
log(" -limit N\n");
log(" only perform the first N combines, then stop. useful for debugging.\n");
log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
log_header(design, "Executing OPT_LUT pass (optimize LUTs).\n"); log_header(design, "Executing OPT_LUT pass (optimize LUTs).\n");
dict<IdString, dict<int, IdString>> dlogic; dict<IdString, dict<int, IdString>> dlogic;
int limit = -1;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
{ {
if (args[argidx] == "-dlogic" && argidx+1 < args.size()) { if (args[argidx] == "-dlogic" && argidx+1 < args.size())
{
std::vector<std::string> tokens; std::vector<std::string> tokens;
split(tokens, args[++argidx], ':'); split(tokens, args[++argidx], ':');
if (tokens.size() < 2) if (tokens.size() < 2)
@ -458,6 +471,11 @@ struct OptLutPass : public Pass {
} }
continue; continue;
} }
if (args[argidx] == "-limit" && argidx + 1 < args.size())
{
limit = atoi(args[++argidx].c_str());
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
@ -465,7 +483,7 @@ struct OptLutPass : public Pass {
int total_count = 0; int total_count = 0;
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
OptLutWorker worker(dlogic, module); OptLutWorker worker(dlogic, module, limit - total_count);
total_count += worker.combined_count; total_count += worker.combined_count;
} }
if (total_count) if (total_count)