mirror of https://github.com/YosysHQ/yosys.git
connect: Do interpret selection arguments
Instead of silently ignoring what would ordinarily be the selection arguments to a pass, interpret those and mark the support in the help message.
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bbb8ad5997
commit
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@ -47,7 +47,7 @@ struct ConnectPass : public Pass {
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{
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log("\n");
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log(" connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr>\n");
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log(" connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr> [selection]\n");
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log("\n");
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log("\n");
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log("Create a connection. This is equivalent to adding the statement 'assign\n");
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log("Create a connection. This is equivalent to adding the statement 'assign\n");
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log("<lhs-expr> = <rhs-expr>;' to the Verilog input. Per default, all existing\n");
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log("<lhs-expr> = <rhs-expr>;' to the Verilog input. Per default, all existing\n");
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@ -55,12 +55,12 @@ struct ConnectPass : public Pass {
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log("the -nounset option.\n");
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log("the -nounset option.\n");
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log("\n");
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log("\n");
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log("\n");
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log("\n");
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log(" connect [-nomap] -unset <expr>\n");
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log(" connect [-nomap] -unset <expr> [selection]\n");
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log("\n");
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log("\n");
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log("Unconnect all existing drivers for the specified expression.\n");
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log("Unconnect all existing drivers for the specified expression.\n");
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log("\n");
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log("\n");
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log("\n");
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log("\n");
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log(" connect [-nomap] [-assert] -port <cell> <port> <expr>\n");
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log(" connect [-nomap] [-assert] -port <cell> <port> <expr> [selection]\n");
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log("\n");
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log("\n");
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log("Connect the specified cell port to the specified cell port.\n");
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log("Connect the specified cell port to the specified cell port.\n");
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log("\n");
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log("\n");
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@ -80,17 +80,6 @@ struct ConnectPass : public Pass {
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}
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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{
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RTLIL::Module *module = nullptr;
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for (auto mod : design->selected_modules()) {
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if (module != nullptr)
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log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name));
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module = mod;
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}
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if (module == nullptr)
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log_cmd_error("No modules selected.\n");
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if (!module->processes.empty())
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log_cmd_error("Found processes in selected module.\n");
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bool flag_nounset = false, flag_nomap = false, flag_assert = false;
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bool flag_nounset = false, flag_nomap = false, flag_assert = false;
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std::string set_lhs, set_rhs, unset_expr;
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std::string set_lhs, set_rhs, unset_expr;
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std::string port_cell, port_port, port_expr;
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std::string port_cell, port_port, port_expr;
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@ -128,6 +117,18 @@ struct ConnectPass : public Pass {
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}
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}
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break;
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break;
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}
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}
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extra_args(args, argidx, design);
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RTLIL::Module *module = nullptr;
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for (auto mod : design->selected_modules()) {
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if (module != nullptr)
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log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name));
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module = mod;
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}
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if (module == nullptr)
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log_cmd_error("No modules selected.\n");
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if (!module->processes.empty())
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log_cmd_error("Found processes in selected module.\n");
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SigMap sigmap;
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SigMap sigmap;
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if (!flag_nomap)
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if (!flag_nomap)
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