Merge automatic and manual code changes for new cell connections API

backends/blif/blif.cc

@@ -146,56 +146,56 @@ struct BlifDumper
 
 			if (!config->icells_mode && cell->type == "$_INV_") {
 				fprintf(f, ".names %s %s\n0 1\n",
-						cstr(cell->connections_.at("\\A")), cstr(cell->connections_.at("\\Y")));
+						cstr(cell->get("\\A")), cstr(cell->get("\\Y")));
 				continue;
 			}
 
 			if (!config->icells_mode && cell->type == "$_AND_") {
 				fprintf(f, ".names %s %s %s\n11 1\n",
-						cstr(cell->connections_.at("\\A")), cstr(cell->connections_.at("\\B")), cstr(cell->connections_.at("\\Y")));
+						cstr(cell->get("\\A")), cstr(cell->get("\\B")), cstr(cell->get("\\Y")));
 				continue;
 			}
 
 			if (!config->icells_mode && cell->type == "$_OR_") {
 				fprintf(f, ".names %s %s %s\n1- 1\n-1 1\n",
-						cstr(cell->connections_.at("\\A")), cstr(cell->connections_.at("\\B")), cstr(cell->connections_.at("\\Y")));
+						cstr(cell->get("\\A")), cstr(cell->get("\\B")), cstr(cell->get("\\Y")));
 				continue;
 			}
 
 			if (!config->icells_mode && cell->type == "$_XOR_") {
 				fprintf(f, ".names %s %s %s\n10 1\n01 1\n",
-						cstr(cell->connections_.at("\\A")), cstr(cell->connections_.at("\\B")), cstr(cell->connections_.at("\\Y")));
+						cstr(cell->get("\\A")), cstr(cell->get("\\B")), cstr(cell->get("\\Y")));
 				continue;
 			}
 
 			if (!config->icells_mode && cell->type == "$_MUX_") {
 				fprintf(f, ".names %s %s %s %s\n1-0 1\n-11 1\n",
-						cstr(cell->connections_.at("\\A")), cstr(cell->connections_.at("\\B")),
+						cstr(cell->get("\\A")), cstr(cell->get("\\B")),
-						cstr(cell->connections_.at("\\S")), cstr(cell->connections_.at("\\Y")));
+						cstr(cell->get("\\S")), cstr(cell->get("\\Y")));
 				continue;
 			}
 
 			if (!config->icells_mode && cell->type == "$_DFF_N_") {
 				fprintf(f, ".latch %s %s fe %s\n",
-						cstr(cell->connections_.at("\\D")), cstr(cell->connections_.at("\\Q")), cstr(cell->connections_.at("\\C")));
+						cstr(cell->get("\\D")), cstr(cell->get("\\Q")), cstr(cell->get("\\C")));
 				continue;
 			}
 
 			if (!config->icells_mode && cell->type == "$_DFF_P_") {
 				fprintf(f, ".latch %s %s re %s\n",
-						cstr(cell->connections_.at("\\D")), cstr(cell->connections_.at("\\Q")), cstr(cell->connections_.at("\\C")));
+						cstr(cell->get("\\D")), cstr(cell->get("\\Q")), cstr(cell->get("\\C")));
 				continue;
 			}
 
 			if (!config->icells_mode && cell->type == "$lut") {
 				fprintf(f, ".names");
-				auto &inputs = cell->connections_.at("\\I");
+				auto &inputs = cell->get("\\I");
 				auto width = cell->parameters.at("\\WIDTH").as_int();
 				log_assert(inputs.size() == width);
 				for (int i = 0; i < inputs.size(); i++) {
 					fprintf(f, " %s", cstr(inputs.extract(i, 1)));
 				}
-				auto &output = cell->connections_.at("\\O");
+				auto &output = cell->get("\\O");
 				log_assert(output.size() == 1);
 				fprintf(f, " %s", cstr(output));
 				fprintf(f, "\n");
@@ -211,7 +211,7 @@ struct BlifDumper
 			}
 
 			fprintf(f, ".%s %s", subckt_or_gate(cell->type), cstr(cell->type));
-			for (auto &conn : cell->connections_)
+			for (auto &conn : cell->connections())
 			for (int i = 0; i < conn.second.size(); i++) {
 				if (conn.second.size() == 1)
 					fprintf(f, " %s", cstr(conn.first));
@@ -240,7 +240,7 @@ struct BlifDumper
 				}
 		}
 
-		for (auto &conn : module->connections_)
+		for (auto &conn : module->connections())
 		for (int i = 0; i < conn.first.size(); i++)
 			if (config->conn_mode)
 				fprintf(f, ".conn %s %s\n", cstr(conn.second.extract(i, 1)), cstr(conn.first.extract(i, 1)));

backends/btor/btor.cc

@@ -193,7 +193,7 @@ struct BtorDumper
 						break;
 					log(" -- found cell %s\n", cstr(cell_id));
 					RTLIL::Cell* cell = module->cells.at(cell_id);
-					RTLIL::SigSpec* cell_output = get_cell_output(cell);
+					const RTLIL::SigSpec* cell_output = get_cell_output(cell);
 					int cell_line = dump_cell(cell);				
 
 					if(dep_set.size()==1 && wire->width == cell_output->size())
@@ -387,8 +387,8 @@ struct BtorDumper
 			if(cell->type == "$assert")
 			{
 				log("writing assert cell - %s\n", cstr(cell->type));
-				const RTLIL::SigSpec* expr = &cell->connections_.at(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* expr = &cell->connections().at(RTLIL::IdString("\\A"));
-				const RTLIL::SigSpec* en = &cell->connections_.at(RTLIL::IdString("\\EN"));
+				const RTLIL::SigSpec* en = &cell->connections().at(RTLIL::IdString("\\EN"));
 				log_assert(expr->size() == 1);
 				log_assert(en->size() == 1);
 				int expr_line = dump_sigspec(expr, 1);
@@ -420,7 +420,7 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				w = w>output_width ? w:output_width; //padding of w
-				int l = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), w);				
+				int l = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), w);				
 				int cell_line = l;
 				if(cell->type != "$pos")
 				{	
@@ -444,7 +444,7 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output_width == 1);
-				int l = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), w);
+				int l = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), w);
 				if(cell->type == "$logic_not" && w > 1)
 				{
 					++line_num;
@@ -481,8 +481,8 @@ struct BtorDumper
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
-				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), l1_width);
+				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), l2_width);
+				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type);
@@ -515,8 +515,8 @@ struct BtorDumper
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
-				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), l1_width);
+				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), l2_width);
+				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type);
@@ -550,8 +550,8 @@ struct BtorDumper
 				l1_width = pow(2, ceil(log(l1_width)/log(2)));
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				//assert(l2_width <= ceil(log(l1_width)/log(2)) );
-				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), l1_width);
+				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
+				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
 				int cell_output = ++line_num;
 				str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), l1_width, l1, l2);
 				fprintf(f, "%s\n", str.c_str());
@@ -559,7 +559,7 @@ struct BtorDumper
 				if(l2_width > ceil(log(l1_width)/log(2)))
 				{
 					int extra_width = l2_width - ceil(log(l1_width)/log(2));
-					l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), l2_width);
+					l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), l2_width);
 					++line_num;
 					str = stringf ("%d slice %d %d %d %d;6", line_num, extra_width, l2, l2_width-1, l2_width-extra_width);
 					fprintf(f, "%s\n", str.c_str());
@@ -592,8 +592,8 @@ struct BtorDumper
 				log("writing binary cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output_width == 1);
-				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), output_width);
+				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), output_width);
-				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), output_width);
+				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), output_width);
 				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				if(l1_width >1)
@@ -628,9 +628,9 @@ struct BtorDumper
 			{
 				log("writing mux cell\n");
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
-				int l1 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\A")), output_width);
+				int l1 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\A")), output_width);
-				int l2 = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\B")), output_width);
+				int l2 = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\B")), output_width);
-				int s = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\S")), 1);
+				int s = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\S")), 1);
 				++line_num;
 				str = stringf ("%d %s %d %d %d %d", 
 					line_num, cell_type_translation.at(cell->type).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
@@ -644,10 +644,10 @@ struct BtorDumper
 				log("writing cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				log(" - width is %d\n", output_width);
-				int cond = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\CLK")), 1);
+				int cond = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-				const RTLIL::SigSpec* cell_output = &cell->connections_.at(RTLIL::IdString("\\Q"));
+				const RTLIL::SigSpec* cell_output = &cell->connections().at(RTLIL::IdString("\\Q"));
-				int value = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\D")), output_width);
+				int value = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\D")), output_width);
 				unsigned start_bit = 0;
 				for(unsigned i=0; i<cell_output->chunks().size(); ++i)
 				{
@@ -665,9 +665,9 @@ struct BtorDumper
 					}
 					if(cell->type == "$dffsr")
 					{
-						int sync_reset = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\CLR")), 1);
+						int sync_reset = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLR")), 1);
 						bool sync_reset_pol = cell->parameters.at(RTLIL::IdString("\\CLR_POLARITY")).as_bool();
-						int sync_reset_value = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\SET")),
+						int sync_reset_value = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\SET")),
 							output_width);
 						bool sync_reset_value_pol = cell->parameters.at(RTLIL::IdString("\\SET_POLARITY")).as_bool();
 						++line_num;
@@ -685,7 +685,7 @@ struct BtorDumper
 					int next = line_num;
 					if(cell->type == "$adff")
 					{
-						int async_reset = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\ARST")), 1);
+						int async_reset = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ARST")), 1);
 						bool async_reset_pol = cell->parameters.at(RTLIL::IdString("\\ARST_POLARITY")).as_bool();
 						int async_reset_value = dump_const(&cell->parameters.at(RTLIL::IdString("\\ARST_VALUE")),
 							output_width, 0);
@@ -710,7 +710,7 @@ struct BtorDumper
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
-				int address = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\ADDR")), address_width);
+				int address = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				++line_num;
 				str = stringf("%d read %d %d %d", line_num, data_width, mem, address);	
@@ -722,13 +722,13 @@ struct BtorDumper
 				log("writing memwr cell\n");
 				if (cell->parameters.at("\\CLK_ENABLE").as_bool() == false)
 					log_error("The btor backen does not support $memwr cells without built-in registers. Run memory_dff (but with -wr_only).\n");
-				int clk = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\CLK")), 1);
+				int clk = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-				int enable = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\EN")), 1);
+				int enable = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\EN")), 1);
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
-				int address = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\ADDR")), address_width);
+				int address = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
-				int data = dump_sigspec(&cell->connections_.at(RTLIL::IdString("\\DATA")), data_width);
+				int data = dump_sigspec(&cell->connections().at(RTLIL::IdString("\\DATA")), data_width);
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				++line_num;
@@ -757,11 +757,11 @@ struct BtorDumper
 			else if(cell->type == "$slice")
 			{
 				log("writing slice cell\n");
-				const RTLIL::SigSpec* input = &cell->connections_.at(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* input = &cell->connections().at(RTLIL::IdString("\\A"));
 				int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				log_assert(input->size() == input_width);
 				int input_line = dump_sigspec(input, input_width);
-				const RTLIL::SigSpec* output = &cell->connections_.at(RTLIL::IdString("\\Y"));
+				const RTLIL::SigSpec* output = &cell->connections().at(RTLIL::IdString("\\Y"));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output->size() == output_width);
 				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();	
@@ -773,11 +773,11 @@ struct BtorDumper
 			else if(cell->type == "$concat")
 			{
 				log("writing concat cell\n");
-				const RTLIL::SigSpec* input_a = &cell->connections_.at(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* input_a = &cell->connections().at(RTLIL::IdString("\\A"));
 				int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				log_assert(input_a->size() == input_a_width);
 				int input_a_line = dump_sigspec(input_a, input_a_width);
-				const RTLIL::SigSpec* input_b = &cell->connections_.at(RTLIL::IdString("\\B"));
+				const RTLIL::SigSpec* input_b = &cell->connections().at(RTLIL::IdString("\\B"));
 				int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				log_assert(input_b->size() == input_b_width);
 				int input_b_line = dump_sigspec(input_b, input_b_width);
@@ -796,12 +796,12 @@ struct BtorDumper
 		}
 	}
 
-	RTLIL::SigSpec* get_cell_output(RTLIL::Cell* cell)
+	const RTLIL::SigSpec* get_cell_output(RTLIL::Cell* cell)
 	{
-		RTLIL::SigSpec *output_sig = nullptr;
+		const RTLIL::SigSpec *output_sig = nullptr;
 		if (cell->type == "$memrd")
 		{
-			output_sig = &cell->connections_.at(RTLIL::IdString("\\DATA"));
+			output_sig = &cell->connections().at(RTLIL::IdString("\\DATA"));
 		}
 		else if(cell->type == "$memwr" || cell->type == "$assert")
 		{
@@ -809,11 +809,11 @@ struct BtorDumper
 		}
 		else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
 		{
-			output_sig = &cell->connections_.at(RTLIL::IdString("\\Q"));
+			output_sig = &cell->connections().at(RTLIL::IdString("\\Q"));
 		}
 		else 
 		{
-			output_sig = &cell->connections_.at(RTLIL::IdString("\\Y"));
+			output_sig = &cell->connections().at(RTLIL::IdString("\\Y"));
 		}
 		return output_sig;
 	}
@@ -835,7 +835,7 @@ struct BtorDumper
 		for (auto it = module->cells.begin(); it != module->cells.end(); ++it)
 		{
 			RTLIL::Cell *cell = it->second;
-			RTLIL::SigSpec* output_sig = get_cell_output(cell);
+			const RTLIL::SigSpec* output_sig = get_cell_output(cell);
 			if(output_sig==nullptr)
 				continue;
 			RTLIL::SigSpec s = sigmap(*output_sig);

backends/edif/edif.cc

@@ -148,7 +148,7 @@ struct EdifBackend : public Backend {
 				RTLIL::Cell *cell = cell_it.second;
 				if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) {
 					lib_cell_ports[cell->type];
-					for (auto p : cell->connections_) {
+					for (auto p : cell->connections()) {
 						if (p.second.size() > 1)
 							log_error("Found multi-bit port %s on library cell %s.%s (%s): not supported in EDIF backend!\n",
 									RTLIL::id2cstr(p.first), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
@@ -304,7 +304,7 @@ struct EdifBackend : public Backend {
 						fprintf(f, "\n            (property %s (string \"%s\"))", EDIF_DEF(p.first), hex_string.c_str());
 					}
 				fprintf(f, ")\n");
-				for (auto &p : cell->connections_) {
+				for (auto &p : cell->connections()) {
 					RTLIL::SigSpec sig = sigmap(p.second);
 					for (int i = 0; i < SIZE(sig); i++)
 						if (sig.size() == 1)

backends/ilang/ilang_backend.cc

@@ -163,7 +163,7 @@ void ILANG_BACKEND::dump_cell(FILE *f, std::string indent, const RTLIL::Cell *ce
 		dump_const(f, it->second);
 		fprintf(f, "\n");
 	}
-	for (auto it = cell->connections_.begin(); it != cell->connections_.end(); it++) {
+	for (auto it = cell->connections().begin(); it != cell->connections().end(); it++) {
 		fprintf(f, "%s  connect %s ", indent.c_str(), it->first.c_str());
 		dump_sigspec(f, it->second);
 		fprintf(f, "\n");
@@ -309,7 +309,7 @@ void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module
 			}
 
 		bool first_conn_line = true;
-		for (auto it = module->connections_.begin(); it != module->connections_.end(); it++) {
+		for (auto it = module->connections().begin(); it != module->connections().end(); it++) {
 			bool show_conn = !only_selected;
 			if (only_selected) {
 				RTLIL::SigSpec sigs = it->first;

backends/intersynth/intersynth.cc

@@ -169,7 +169,7 @@ struct IntersynthBackend : public Backend {
 
 				celltype_code = stringf("celltype %s", RTLIL::id2cstr(cell->type));
 				node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
-				for (auto &port : cell->connections_) {
+				for (auto &port : cell->connections()) {
 					RTLIL::SigSpec sig = sigmap(port.second);
 					if (sig.size() != 0) {
 						conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));

backends/spice/spice.cc

@@ -58,7 +58,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
 		{
 			log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
 					RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name));
-			for (auto &conn : cell->connections_) {
+			for (auto &conn : cell->connections()) {
 				RTLIL::SigSpec sig = sigmap(conn.second);
 				port_sigs.push_back(sig);
 			}
@@ -80,8 +80,8 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
 			for (RTLIL::Wire *wire : ports) {
 				log_assert(wire != NULL);
 				RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
-				if (cell->connections_.count(wire->name) > 0) {
+				if (cell->connections().count(wire->name) > 0) {
-					sig = sigmap(cell->connections_.at(wire->name));
+					sig = sigmap(cell->connections().at(wire->name));
 					sig.extend(wire->width, false);
 				}
 				port_sigs.push_back(sig);
@@ -98,7 +98,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
 		fprintf(f, " %s\n", RTLIL::id2cstr(cell->type));
 	}
 
-	for (auto &conn : module->connections_)
+	for (auto &conn : module->connections())
 	for (int i = 0; i < conn.first.size(); i++) {
 		fprintf(f, "V%d", conn_counter++);
 		print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter);

backends/verilog/verilog_backend.cc

@@ -223,7 +223,7 @@ void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = fals
 	}
 }
 
-void dump_sigspec(FILE *f, RTLIL::SigSpec &sig)
+void dump_sigspec(FILE *f, const RTLIL::SigSpec &sig)
 {
 	if (sig.is_chunk()) {
 		dump_sigchunk(f, sig.as_chunk());
@@ -293,17 +293,17 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_
 {
 	if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) {
 		fprintf(f, "$signed(");
-		dump_sigspec(f, cell->connections_["\\" + port]);
+		dump_sigspec(f, cell->get("\\" + port));
 		fprintf(f, ")");
 	} else
-		dump_sigspec(f, cell->connections_["\\" + port]);
+		dump_sigspec(f, cell->get("\\" + port));
 }
 
 std::string cellname(RTLIL::Cell *cell)
 {
-	if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections_.count("\\Q") > 0)
+	if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections().count("\\Q") > 0)
 	{
-		RTLIL::SigSpec sig = cell->connections_["\\Q"];
+		RTLIL::SigSpec sig = cell->get("\\Q");
 		if (SIZE(sig) != 1 || sig.is_fully_const())
 			goto no_special_reg_name;
 
@@ -338,7 +338,7 @@ no_special_reg_name:
 void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op)
 {
 	fprintf(f, "%s" "assign ", indent.c_str());
-	dump_sigspec(f, cell->connections_["\\Y"]);
+	dump_sigspec(f, cell->get("\\Y"));
 	fprintf(f, " = %s ", op.c_str());
 	dump_attributes(f, "", cell->attributes, ' ');
 	dump_cell_expr_port(f, cell, "A", true);
@@ -348,7 +348,7 @@ void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::s
 void dump_cell_expr_binop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op)
 {
 	fprintf(f, "%s" "assign ", indent.c_str());
-	dump_sigspec(f, cell->connections_["\\Y"]);
+	dump_sigspec(f, cell->get("\\Y"));
 	fprintf(f, " = ");
 	dump_cell_expr_port(f, cell, "A", true);
 	fprintf(f, " %s ", op.c_str());
@@ -361,7 +361,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 {
 	if (cell->type == "$_INV_") {
 		fprintf(f, "%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->connections_["\\Y"]);
+		dump_sigspec(f, cell->get("\\Y"));
 		fprintf(f, " = ");
 		fprintf(f, "~");
 		dump_attributes(f, "", cell->attributes, ' ');
@@ -372,7 +372,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 
 	if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") {
 		fprintf(f, "%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->connections_["\\Y"]);
+		dump_sigspec(f, cell->get("\\Y"));
 		fprintf(f, " = ");
 		dump_cell_expr_port(f, cell, "A", false);
 		fprintf(f, " ");
@@ -391,7 +391,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 
 	if (cell->type == "$_MUX_") {
 		fprintf(f, "%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->connections_["\\Y"]);
+		dump_sigspec(f, cell->get("\\Y"));
 		fprintf(f, " = ");
 		dump_cell_expr_port(f, cell, "S", false);
 		fprintf(f, " ? ");
@@ -406,23 +406,23 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 	if (cell->type.substr(0, 6) == "$_DFF_")
 	{
 		std::string reg_name = cellname(cell);
-		bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name);
+		bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name);
 
 		if (!out_is_reg_wire)
 			fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str());
 
 		dump_attributes(f, indent, cell->attributes);
 		fprintf(f, "%s" "always @(%sedge ", indent.c_str(), cell->type[6] == 'P' ? "pos" : "neg");
-		dump_sigspec(f, cell->connections_["\\C"]);
+		dump_sigspec(f, cell->get("\\C"));
 		if (cell->type[7] != '_') {
 			fprintf(f, " or %sedge ", cell->type[7] == 'P' ? "pos" : "neg");
-			dump_sigspec(f, cell->connections_["\\R"]);
+			dump_sigspec(f, cell->get("\\R"));
 		}
 		fprintf(f, ")\n");
 
 		if (cell->type[7] != '_') {
 			fprintf(f, "%s" "  if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!");
-			dump_sigspec(f, cell->connections_["\\R"]);
+			dump_sigspec(f, cell->get("\\R"));
 			fprintf(f, ")\n");
 			fprintf(f, "%s" "    %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]);
 			fprintf(f, "%s" "  else\n", indent.c_str());
@@ -434,7 +434,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 
 		if (!out_is_reg_wire) {
 			fprintf(f, "%s" "assign ", indent.c_str());
-			dump_sigspec(f, cell->connections_["\\Q"]);
+			dump_sigspec(f, cell->get("\\Q"));
 			fprintf(f, " = %s;\n", reg_name.c_str());
 		}
 
@@ -446,27 +446,27 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 		char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10];
 
 		std::string reg_name = cellname(cell);
-		bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name);
+		bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name);
 
 		if (!out_is_reg_wire)
 			fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str());
 
 		dump_attributes(f, indent, cell->attributes);
 		fprintf(f, "%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg");
-		dump_sigspec(f, cell->connections_["\\C"]);
+		dump_sigspec(f, cell->get("\\C"));
 		fprintf(f, " or %sedge ", pol_s == 'P' ? "pos" : "neg");
-		dump_sigspec(f, cell->connections_["\\S"]);
+		dump_sigspec(f, cell->get("\\S"));
 		fprintf(f, " or %sedge ", pol_r == 'P' ? "pos" : "neg");
-		dump_sigspec(f, cell->connections_["\\R"]);
+		dump_sigspec(f, cell->get("\\R"));
 		fprintf(f, ")\n");
 
 		fprintf(f, "%s" "  if (%s", indent.c_str(), pol_r == 'P' ? "" : "!");
-		dump_sigspec(f, cell->connections_["\\R"]);
+		dump_sigspec(f, cell->get("\\R"));
 		fprintf(f, ")\n");
 		fprintf(f, "%s" "    %s <= 0;\n", indent.c_str(), reg_name.c_str());
 
 		fprintf(f, "%s" "  else if (%s", indent.c_str(), pol_s == 'P' ? "" : "!");
-		dump_sigspec(f, cell->connections_["\\S"]);
+		dump_sigspec(f, cell->get("\\S"));
 		fprintf(f, ")\n");
 		fprintf(f, "%s" "    %s <= 1;\n", indent.c_str(), reg_name.c_str());
 
@@ -477,7 +477,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 
 		if (!out_is_reg_wire) {
 			fprintf(f, "%s" "assign ", indent.c_str());
-			dump_sigspec(f, cell->connections_["\\Q"]);
+			dump_sigspec(f, cell->get("\\Q"));
 			fprintf(f, " = %s;\n", reg_name.c_str());
 		}
 
@@ -535,7 +535,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 	if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe")
 	{
 		int width = cell->parameters["\\WIDTH"].as_int();
-		int s_width = cell->connections_["\\S"].size();
+		int s_width = cell->get("\\S").size();
 		std::string func_name = cellname(cell);
 
 		fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str());
@@ -567,13 +567,13 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 		fprintf(f, "%s" "endfunction\n", indent.c_str());
 
 		fprintf(f, "%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->connections_["\\Y"]);
+		dump_sigspec(f, cell->get("\\Y"));
 		fprintf(f, " = %s(", func_name.c_str());
-		dump_sigspec(f, cell->connections_["\\A"]);
+		dump_sigspec(f, cell->get("\\A"));
 		fprintf(f, ", ");
-		dump_sigspec(f, cell->connections_["\\B"]);
+		dump_sigspec(f, cell->get("\\B"));
 		fprintf(f, ", ");
-		dump_sigspec(f, cell->connections_["\\S"]);
+		dump_sigspec(f, cell->get("\\S"));
 		fprintf(f, ");\n");
 		return true;
 	}
@@ -581,9 +581,9 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 	if (cell->type == "$slice")
 	{
 		fprintf(f, "%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->connections_["\\Y"]);
+		dump_sigspec(f, cell->get("\\Y"));
 		fprintf(f, " = ");
-		dump_sigspec(f, cell->connections_["\\A"]);
+		dump_sigspec(f, cell->get("\\A"));
 		fprintf(f, " >> %d;\n", cell->parameters.at("\\OFFSET").as_int());
 		return true;
 	}
@@ -591,14 +591,14 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 	if (cell->type == "$bu0")
 	{
 		fprintf(f, "%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->connections_["\\Y"]);
+		dump_sigspec(f, cell->get("\\Y"));
 		if (cell->parameters["\\A_SIGNED"].as_bool()) {
 			fprintf(f, " = $signed(");
-			dump_sigspec(f, cell->connections_["\\A"]);
+			dump_sigspec(f, cell->get("\\A"));
 			fprintf(f, ");\n");
 		} else {
 			fprintf(f, " = { 1'b0, ");
-			dump_sigspec(f, cell->connections_["\\A"]);
+			dump_sigspec(f, cell->get("\\A"));
 			fprintf(f, " };\n");
 		}
 		return true;
@@ -607,11 +607,11 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 	if (cell->type == "$concat")
 	{
 		fprintf(f, "%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->connections_["\\Y"]);
+		dump_sigspec(f, cell->get("\\Y"));
 		fprintf(f, " = { ");
-		dump_sigspec(f, cell->connections_["\\B"]);
+		dump_sigspec(f, cell->get("\\B"));
 		fprintf(f, " , ");
-		dump_sigspec(f, cell->connections_["\\A"]);
+		dump_sigspec(f, cell->get("\\A"));
 		fprintf(f, " };\n");
 		return true;
 	}
@@ -621,17 +621,17 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 		RTLIL::SigSpec sig_clk, sig_arst, val_arst;
 		bool pol_clk, pol_arst = false;
 
-		sig_clk = cell->connections_["\\CLK"];
+		sig_clk = cell->get("\\CLK");
 		pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool();
 
 		if (cell->type == "$adff") {
-			sig_arst = cell->connections_["\\ARST"];
+			sig_arst = cell->get("\\ARST");
 			pol_arst = cell->parameters["\\ARST_POLARITY"].as_bool();
 			val_arst = RTLIL::SigSpec(cell->parameters["\\ARST_VALUE"]);
 		}
 
 		std::string reg_name = cellname(cell);
-		bool out_is_reg_wire = is_reg_wire(cell->connections_["\\Q"], reg_name);
+		bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name);
 
 		if (!out_is_reg_wire)
 			fprintf(f, "%s" "reg [%d:0] %s;\n", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str());
@@ -660,7 +660,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 
 		if (!out_is_reg_wire) {
 			fprintf(f, "%s" "assign ", indent.c_str());
-			dump_sigspec(f, cell->connections_["\\Q"]);
+			dump_sigspec(f, cell->get("\\Q"));
 			fprintf(f, " = %s;\n", reg_name.c_str());
 		}
 
@@ -707,7 +707,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell)
 	for (int i = 1; true; i++) {
 		char str[16];
 		snprintf(str, 16, "$%d", i);
-		for (auto it = cell->connections_.begin(); it != cell->connections_.end(); it++) {
+		for (auto it = cell->connections().begin(); it != cell->connections().end(); it++) {
 			if (it->first != str)
 				continue;
 			if (!first_arg)
@@ -721,7 +721,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell)
 		break;
 	found_numbered_port:;
 	}
-	for (auto it = cell->connections_.begin(); it != cell->connections_.end(); it++) {
+	for (auto it = cell->connections().begin(); it != cell->connections().end(); it++) {
 		if (numbered_ports.count(it->first))
 			continue;
 		if (!first_arg)
@@ -735,7 +735,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell)
 	fprintf(f, "\n%s" ");\n", indent.c_str());
 }
 
-void dump_conn(FILE *f, std::string indent, RTLIL::SigSpec &left, RTLIL::SigSpec &right)
+void dump_conn(FILE *f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
 {
 	fprintf(f, "%s" "assign ", indent.c_str());
 	dump_sigspec(f, left);
@@ -908,10 +908,10 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
 		for (auto &it : module->cells)
 		{
 			RTLIL::Cell *cell = it.second;
-			if (!reg_ct.cell_known(cell->type) || cell->connections_.count("\\Q") == 0)
+			if (!reg_ct.cell_known(cell->type) || cell->connections().count("\\Q") == 0)
 				continue;
 
-			RTLIL::SigSpec sig = cell->connections_["\\Q"];
+			RTLIL::SigSpec sig = cell->get("\\Q");
 
 			if (sig.is_chunk()) {
 				RTLIL::SigChunk chunk = sig.as_chunk();
@@ -961,7 +961,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
 	for (auto it = module->processes.begin(); it != module->processes.end(); it++)
 		dump_process(f, indent + "  ", it->second);
 
-	for (auto it = module->connections_.begin(); it != module->connections_.end(); it++)
+	for (auto it = module->connections().begin(); it != module->connections().end(); it++)
 		dump_conn(f, indent + "  ", it->first, it->second);
 
 	fprintf(f, "%s" "endmodule\n", indent.c_str());

frontends/ast/genrtlil.cc

@@ -60,10 +60,10 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
 
 	cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
 	cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
-	cell->connections_["\\A"] = arg;
+	cell->set("\\A", arg);
 
 	cell->parameters["\\Y_WIDTH"] = result_width;
-	cell->connections_["\\Y"] = wire;
+	cell->set("\\Y", wire);
 	return wire;
 }
 
@@ -94,10 +94,10 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
 
 	cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
 	cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
-	cell->connections_["\\A"] = sig;
+	cell->set("\\A", sig);
 
 	cell->parameters["\\Y_WIDTH"] = width;
-	cell->connections_["\\Y"] = wire;
+	cell->set("\\Y", wire);
 	sig = wire;
 }
 
@@ -126,11 +126,11 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
 	cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
 	cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
 
-	cell->connections_["\\A"] = left;
+	cell->set("\\A", left);
-	cell->connections_["\\B"] = right;
+	cell->set("\\B", right);
 
 	cell->parameters["\\Y_WIDTH"] = result_width;
-	cell->connections_["\\Y"] = wire;
+	cell->set("\\Y", wire);
 	return wire;
 }
 
@@ -157,10 +157,10 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
 
 	cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
 
-	cell->connections_["\\A"] = right;
+	cell->set("\\A", right);
-	cell->connections_["\\B"] = left;
+	cell->set("\\B", left);
-	cell->connections_["\\S"] = cond;
+	cell->set("\\S", cond);
-	cell->connections_["\\Y"] = wire;
+	cell->set("\\Y", wire);
 
 	return wire;
 }
@@ -1169,9 +1169,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			while ((1 << addr_bits) < current_module->memories[str]->size)
 				addr_bits++;
 
-			cell->connections_["\\CLK"] = RTLIL::SigSpec(RTLIL::State::Sx, 1);
+			cell->set("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
-			cell->connections_["\\ADDR"] = children[0]->genWidthRTLIL(addr_bits);
+			cell->set("\\ADDR", children[0]->genWidthRTLIL(addr_bits));
-			cell->connections_["\\DATA"] = RTLIL::SigSpec(wire);
+			cell->set("\\DATA", RTLIL::SigSpec(wire));
 
 			cell->parameters["\\MEMID"] = RTLIL::Const(str);
 			cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
@@ -1197,10 +1197,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			while ((1 << addr_bits) < current_module->memories[str]->size)
 				addr_bits++;
 
-			cell->connections_["\\CLK"] = RTLIL::SigSpec(RTLIL::State::Sx, 1);
+			cell->set("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
-			cell->connections_["\\ADDR"] = children[0]->genWidthRTLIL(addr_bits);
+			cell->set("\\ADDR", children[0]->genWidthRTLIL(addr_bits));
-			cell->connections_["\\DATA"] = children[1]->genWidthRTLIL(current_module->memories[str]->width);
+			cell->set("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width));
-			cell->connections_["\\EN"] = children[2]->genRTLIL();
+			cell->set("\\EN", children[2]->genRTLIL());
 
 			cell->parameters["\\MEMID"] = RTLIL::Const(str);
 			cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
@@ -1237,8 +1237,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				cell->attributes[attr.first] = attr.second->asAttrConst();
 			}
 
-			cell->connections_["\\A"] = check;
+			cell->set("\\A", check);
-			cell->connections_["\\EN"] = en;
+			cell->set("\\EN", en);
 		}
 		break;
 
@@ -1248,11 +1248,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			if (children[0]->type == AST_IDENTIFIER && children[0]->id2ast && children[0]->id2ast->type == AST_AUTOWIRE) {
 				RTLIL::SigSpec right = children[1]->genRTLIL();
 				RTLIL::SigSpec left = children[0]->genWidthRTLIL(right.size());
-				current_module->connections_.push_back(RTLIL::SigSig(left, right));
+				current_module->connect(RTLIL::SigSig(left, right));
 			} else {
 				RTLIL::SigSpec left = children[0]->genRTLIL();
 				RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
-				current_module->connections_.push_back(RTLIL::SigSig(left, right));
+				current_module->connect(RTLIL::SigSig(left, right));
 			}
 		}
 		break;
@@ -1297,9 +1297,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					if (child->str.size() == 0) {
 						char buf[100];
 						snprintf(buf, 100, "$%d", ++port_counter);
-						cell->connections_[buf] = sig;
+						cell->set(buf, sig);
 					} else {
-						cell->connections_[child->str] = sig;
+						cell->set(child->str, sig);
 					}
 					continue;
 				}

frontends/ilang/parser.y

@@ -202,9 +202,9 @@ cell_body:
 		delete $5;
 	} |
 	cell_body TOK_CONNECT TOK_ID sigspec EOL {
-		if (current_cell->connections_.count($3) != 0)
+		if (current_cell->connections().count($3) != 0)
 			rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell port %s.", $3).c_str());
-		current_cell->connections_[$3] = *$4;
+		current_cell->set($3, *$4);
 		delete $4;
 		free($3);
 	} |

frontends/liberty/liberty.cc

@@ -55,36 +55,36 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
 static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
 {
 	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
-	cell->connections_["\\A"] = A;
+	cell->set("\\A", A);
-	cell->connections_["\\Y"] = module->addWire(NEW_ID);
+	cell->set("\\Y", module->addWire(NEW_ID));
-	return cell->connections_["\\Y"];
+	return cell->get("\\Y");
 }
 
 static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
 {
 	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_XOR_");
-	cell->connections_["\\A"] = A;
+	cell->set("\\A", A);
-	cell->connections_["\\B"] = B;
+	cell->set("\\B", B);
-	cell->connections_["\\Y"] = module->addWire(NEW_ID);
+	cell->set("\\Y", module->addWire(NEW_ID));
-	return cell->connections_["\\Y"];
+	return cell->get("\\Y");
 }
 
 static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
 {
 	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_AND_");
-	cell->connections_["\\A"] = A;
+	cell->set("\\A", A);
-	cell->connections_["\\B"] = B;
+	cell->set("\\B", B);
-	cell->connections_["\\Y"] = module->addWire(NEW_ID);
+	cell->set("\\Y", module->addWire(NEW_ID));
-	return cell->connections_["\\Y"];
+	return cell->get("\\Y");
 }
 
 static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
 {
 	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_OR_");
-	cell->connections_["\\A"] = A;
+	cell->set("\\A", A);
-	cell->connections_["\\B"] = B;
+	cell->set("\\B", B);
-	cell->connections_["\\Y"] = module->addWire(NEW_ID);
+	cell->set("\\Y", module->addWire(NEW_ID));
-	return cell->connections_["\\Y"];
+	return cell->get("\\Y");
 }
 
 static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack, token_t next_token)
@@ -240,18 +240,18 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
 		rerun_invert_rollback = false;
 
 		for (auto &it : module->cells) {
-			if (it.second->type == "$_INV_" && it.second->connections_.at("\\Y") == clk_sig) {
+			if (it.second->type == "$_INV_" && it.second->get("\\Y") == clk_sig) {
-				clk_sig = it.second->connections_.at("\\A");
+				clk_sig = it.second->get("\\A");
 				clk_polarity = !clk_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == "$_INV_" && it.second->connections_.at("\\Y") == clear_sig) {
+			if (it.second->type == "$_INV_" && it.second->get("\\Y") == clear_sig) {
-				clear_sig = it.second->connections_.at("\\A");
+				clear_sig = it.second->get("\\A");
 				clear_polarity = !clear_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == "$_INV_" && it.second->connections_.at("\\Y") == preset_sig) {
+			if (it.second->type == "$_INV_" && it.second->get("\\Y") == preset_sig) {
-				preset_sig = it.second->connections_.at("\\A");
+				preset_sig = it.second->get("\\A");
 				preset_polarity = !preset_polarity;
 				rerun_invert_rollback = true;
 			}
@@ -259,13 +259,13 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
 	}
 
 	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
-	cell->connections_["\\A"] = iq_sig;
+	cell->set("\\A", iq_sig);
-	cell->connections_["\\Y"] = iqn_sig;
+	cell->set("\\Y", iqn_sig);
 
 	cell = module->addCell(NEW_ID, "");
-	cell->connections_["\\D"] = data_sig;
+	cell->set("\\D", data_sig);
-	cell->connections_["\\Q"] = iq_sig;
+	cell->set("\\Q", iq_sig);
-	cell->connections_["\\C"] = clk_sig;
+	cell->set("\\C", clk_sig);
 
 	if (clear_sig.size() == 0 && preset_sig.size() == 0) {
 		cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
@@ -273,18 +273,18 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
 
 	if (clear_sig.size() == 1 && preset_sig.size() == 0) {
 		cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
-		cell->connections_["\\R"] = clear_sig;
+		cell->set("\\R", clear_sig);
 	}
 
 	if (clear_sig.size() == 0 && preset_sig.size() == 1) {
 		cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N');
-		cell->connections_["\\R"] = preset_sig;
+		cell->set("\\R", preset_sig);
 	}
 
 	if (clear_sig.size() == 1 && preset_sig.size() == 1) {
 		cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
-		cell->connections_["\\S"] = preset_sig;
+		cell->set("\\S", preset_sig);
-		cell->connections_["\\R"] = clear_sig;
+		cell->set("\\R", clear_sig);
 	}
 
 	log_assert(!cell->type.empty());
@@ -317,18 +317,18 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
 		rerun_invert_rollback = false;
 
 		for (auto &it : module->cells) {
-			if (it.second->type == "$_INV_" && it.second->connections_.at("\\Y") == enable_sig) {
+			if (it.second->type == "$_INV_" && it.second->get("\\Y") == enable_sig) {
-				enable_sig = it.second->connections_.at("\\A");
+				enable_sig = it.second->get("\\A");
 				enable_polarity = !enable_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == "$_INV_" && it.second->connections_.at("\\Y") == clear_sig) {
+			if (it.second->type == "$_INV_" && it.second->get("\\Y") == clear_sig) {
-				clear_sig = it.second->connections_.at("\\A");
+				clear_sig = it.second->get("\\A");
 				clear_polarity = !clear_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == "$_INV_" && it.second->connections_.at("\\Y") == preset_sig) {
+			if (it.second->type == "$_INV_" && it.second->get("\\Y") == preset_sig) {
-				preset_sig = it.second->connections_.at("\\A");
+				preset_sig = it.second->get("\\A");
 				preset_polarity = !preset_polarity;
 				rerun_invert_rollback = true;
 			}
@@ -336,8 +336,8 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
 	}
 
 	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
-	cell->connections_["\\A"] = iq_sig;
+	cell->set("\\A", iq_sig);
-	cell->connections_["\\Y"] = iqn_sig;
+	cell->set("\\Y", iqn_sig);
 
 	if (clear_sig.size() == 1)
 	{
@@ -347,24 +347,24 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
 		if (clear_polarity == true || clear_polarity != enable_polarity)
 		{
 			RTLIL::Cell *inv = module->addCell(NEW_ID, "$_INV_");
-			inv->connections_["\\A"] = clear_sig;
+			inv->set("\\A", clear_sig);
-			inv->connections_["\\Y"] = module->addWire(NEW_ID);
+			inv->set("\\Y", module->addWire(NEW_ID));
 
 			if (clear_polarity == true)
-				clear_negative = inv->connections_["\\Y"];
+				clear_negative = inv->get("\\Y");
 			if (clear_polarity != enable_polarity)
-				clear_enable = inv->connections_["\\Y"];
+				clear_enable = inv->get("\\Y");
 		}
 
 		RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_AND_");
-		data_gate->connections_["\\A"] = data_sig;
+		data_gate->set("\\A", data_sig);
-		data_gate->connections_["\\B"] = clear_negative;
+		data_gate->set("\\B", clear_negative);
-		data_gate->connections_["\\Y"] = data_sig = module->addWire(NEW_ID);
+		data_gate->set("\\Y", data_sig = module->addWire(NEW_ID));
 
 		RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
-		enable_gate->connections_["\\A"] = enable_sig;
+		enable_gate->set("\\A", enable_sig);
-		enable_gate->connections_["\\B"] = clear_enable;
+		enable_gate->set("\\B", clear_enable);
-		enable_gate->connections_["\\Y"] = data_sig = module->addWire(NEW_ID);
+		enable_gate->set("\\Y", data_sig = module->addWire(NEW_ID));
 	}
 
 	if (preset_sig.size() == 1)
@@ -375,30 +375,30 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
 		if (preset_polarity == false || preset_polarity != enable_polarity)
 		{
 			RTLIL::Cell *inv = module->addCell(NEW_ID, "$_INV_");
-			inv->connections_["\\A"] = preset_sig;
+			inv->set("\\A", preset_sig);
-			inv->connections_["\\Y"] = module->addWire(NEW_ID);
+			inv->set("\\Y", module->addWire(NEW_ID));
 
 			if (preset_polarity == false)
-				preset_positive = inv->connections_["\\Y"];
+				preset_positive = inv->get("\\Y");
 			if (preset_polarity != enable_polarity)
-				preset_enable = inv->connections_["\\Y"];
+				preset_enable = inv->get("\\Y");
 		}
 
 		RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_OR_");
-		data_gate->connections_["\\A"] = data_sig;
+		data_gate->set("\\A", data_sig);
-		data_gate->connections_["\\B"] = preset_positive;
+		data_gate->set("\\B", preset_positive);
-		data_gate->connections_["\\Y"] = data_sig = module->addWire(NEW_ID);
+		data_gate->set("\\Y", data_sig = module->addWire(NEW_ID));
 
 		RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
-		enable_gate->connections_["\\A"] = enable_sig;
+		enable_gate->set("\\A", enable_sig);
-		enable_gate->connections_["\\B"] = preset_enable;
+		enable_gate->set("\\B", preset_enable);
-		enable_gate->connections_["\\Y"] = data_sig = module->addWire(NEW_ID);
+		enable_gate->set("\\Y", data_sig = module->addWire(NEW_ID));
 	}
 
 	cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
-	cell->connections_["\\D"] = data_sig;
+	cell->set("\\D", data_sig);
-	cell->connections_["\\Q"] = iq_sig;
+	cell->set("\\Q", iq_sig);
-	cell->connections_["\\E"] = enable_sig;
+	cell->set("\\E", enable_sig);
 }
 
 struct LibertyFrontend : public Frontend {
@@ -559,7 +559,7 @@ struct LibertyFrontend : public Frontend {
 					}
 
 					RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
-					module->connections_.push_back(RTLIL::SigSig(wire, out_sig));
+					module->connect(RTLIL::SigSig(wire, out_sig));
 				}
 			}
 

kernel/consteval.h

@@ -43,7 +43,7 @@ struct ConstEval
 		for (auto &it : module->cells) {
 			if (!ct.cell_known(it.second->type))
 				continue;
-			for (auto &it2 : it.second->connections_)
+			for (auto &it2 : it.second->connections())
 				if (ct.cell_output(it.second->type, it2.first))
 					sig2driver.insert(assign_map(it2.second), it.second);
 		}
@@ -87,22 +87,22 @@ struct ConstEval
 	{
 		RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
 
-		assert(cell->connections_.count("\\Y") > 0);
+		assert(cell->connections().count("\\Y") > 0);
-		sig_y = values_map(assign_map(cell->connections_["\\Y"]));
+		sig_y = values_map(assign_map(cell->get("\\Y")));
 		if (sig_y.is_fully_const())
 			return true;
 
-		if (cell->connections_.count("\\S") > 0) {
+		if (cell->connections().count("\\S") > 0) {
-			sig_s = cell->connections_["\\S"];
+			sig_s = cell->get("\\S");
 			if (!eval(sig_s, undef, cell))
 				return false;
 		}
 
-		if (cell->connections_.count("\\A") > 0)
+		if (cell->connections().count("\\A") > 0)
-			sig_a = cell->connections_["\\A"];
+			sig_a = cell->get("\\A");
 
-		if (cell->connections_.count("\\B") > 0)
+		if (cell->connections().count("\\B") > 0)
-			sig_b = cell->connections_["\\B"];
+			sig_b = cell->get("\\B");
 
 		if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_")
 		{

kernel/modwalker.h

@@ -88,12 +88,12 @@ struct ModWalker
 	void add_cell(RTLIL::Cell *cell)
 	{
 		if (ct.cell_known(cell->type)) {
-			for (auto &conn : cell->connections_)
+			for (auto &conn : cell->connections())
 				add_cell_port(cell, conn.first, sigmap(conn.second),
 						ct.cell_output(cell->type, conn.first),
 						ct.cell_input(cell->type, conn.first));
 		} else {
-			for (auto &conn : cell->connections_)
+			for (auto &conn : cell->connections())
 				add_cell_port(cell, conn.first, sigmap(conn.second), true, true);
 		}
 	}

kernel/rtlil.cc

@@ -348,9 +348,9 @@ namespace {
 
 		void port(const char *name, int width)
 		{
-			if (cell->connections_.count(name) == 0)
+			if (cell->connections().count(name) == 0)
 				error(__LINE__);
-			if (cell->connections_.at(name).size() != width)
+			if (cell->connections().at(name).size() != width)
 				error(__LINE__);
 			expected_ports.insert(name);
 		}
@@ -360,7 +360,7 @@ namespace {
 			for (auto &para : cell->parameters)
 				if (expected_params.count(para.first) == 0)
 					error(__LINE__);
-			for (auto &conn : cell->connections_)
+			for (auto &conn : cell->connections())
 				if (expected_ports.count(conn.first) == 0)
 					error(__LINE__);
 
@@ -379,13 +379,13 @@ namespace {
 
 			for (const char *p = ports; *p; p++) {
 				char portname[3] = { '\\', *p, 0 };
-				if (cell->connections_.count(portname) == 0)
+				if (cell->connections().count(portname) == 0)
 					error(__LINE__);
-				if (cell->connections_.at(portname).size() != 1)
+				if (cell->connections().at(portname).size() != 1)
 					error(__LINE__);
 			}
 
-			for (auto &conn : cell->connections_) {
+			for (auto &conn : cell->connections()) {
 				if (conn.first.size() != 2 || conn.first.at(0) != '\\')
 					error(__LINE__);
 				if (strchr(ports, conn.first.at(1)) == NULL)
@@ -734,7 +734,7 @@ void RTLIL::Module::check()
 		assert(it.first == it.second->name);
 		assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 		assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
-		for (auto &it2 : it.second->connections_) {
+		for (auto &it2 : it.second->connections()) {
 			assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
 			it2.second.check();
 		}
@@ -938,8 +938,8 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
 		cell->parameters["\\A_SIGNED"] = is_signed;         \
 		cell->parameters["\\A_WIDTH"] = sig_a.size();        \
 		cell->parameters["\\Y_WIDTH"] = sig_y.size();        \
-		cell->connections_["\\A"] = sig_a;                   \
+		cell->set("\\A", sig_a);                   \
-		cell->connections_["\\Y"] = sig_y;                   \
+		cell->set("\\Y", sig_y);                   \
 		add(cell);                                          \
 		return cell;                                        \
 	} \
@@ -970,9 +970,9 @@ DEF_METHOD(LogicNot,   1, "$logic_not")
 		cell->parameters["\\A_WIDTH"] = sig_a.size();        \
 		cell->parameters["\\B_WIDTH"] = sig_b.size();        \
 		cell->parameters["\\Y_WIDTH"] = sig_y.size();        \
-		cell->connections_["\\A"] = sig_a;                   \
+		cell->set("\\A", sig_a);                   \
-		cell->connections_["\\B"] = sig_b;                   \
+		cell->set("\\B", sig_b);                   \
-		cell->connections_["\\Y"] = sig_y;                   \
+		cell->set("\\Y", sig_y);                   \
 		add(cell);                                          \
 		return cell;                                        \
 	} \
@@ -1014,10 +1014,10 @@ DEF_METHOD(LogicOr,  1, "$logic_or")
 		cell->parameters["\\WIDTH"] = sig_a.size();               \
 		cell->parameters["\\WIDTH"] = sig_b.size();               \
 		if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size();  \
-		cell->connections_["\\A"] = sig_a;                        \
+		cell->set("\\A", sig_a);                        \
-		cell->connections_["\\B"] = sig_b;                        \
+		cell->set("\\B", sig_b);                        \
-		cell->connections_["\\S"] = sig_s;                        \
+		cell->set("\\S", sig_s);                        \
-		cell->connections_["\\Y"] = sig_y;                        \
+		cell->set("\\Y", sig_y);                        \
 		add(cell);                                               \
 		return cell;                                             \
 	} \
@@ -1036,8 +1036,8 @@ DEF_METHOD(SafePmux, "$safe_pmux",  1)
 		RTLIL::Cell *cell = new RTLIL::Cell;        \
 		cell->name = name;                          \
 		cell->type = _type;                         \
-		cell->connections_["\\" #_P1] = sig1;        \
+		cell->set("\\" #_P1, sig1);                 \
-		cell->connections_["\\" #_P2] = sig2;        \
+		cell->set("\\" #_P2, sig2);                 \
 		add(cell);                                  \
 		return cell;                                \
 	} \
@@ -1051,9 +1051,9 @@ DEF_METHOD(SafePmux, "$safe_pmux",  1)
 		RTLIL::Cell *cell = new RTLIL::Cell;        \
 		cell->name = name;                          \
 		cell->type = _type;                         \
-		cell->connections_["\\" #_P1] = sig1;        \
+		cell->set("\\" #_P1, sig1);                 \
-		cell->connections_["\\" #_P2] = sig2;        \
+		cell->set("\\" #_P2, sig2);                 \
-		cell->connections_["\\" #_P3] = sig3;        \
+		cell->set("\\" #_P3, sig3);                 \
 		add(cell);                                  \
 		return cell;                                \
 	} \
@@ -1067,10 +1067,10 @@ DEF_METHOD(SafePmux, "$safe_pmux",  1)
 		RTLIL::Cell *cell = new RTLIL::Cell;        \
 		cell->name = name;                          \
 		cell->type = _type;                         \
-		cell->connections_["\\" #_P1] = sig1;        \
+		cell->set("\\" #_P1, sig1);                 \
-		cell->connections_["\\" #_P2] = sig2;        \
+		cell->set("\\" #_P2, sig2);                 \
-		cell->connections_["\\" #_P3] = sig3;        \
+		cell->set("\\" #_P3, sig3);                 \
-		cell->connections_["\\" #_P4] = sig4;        \
+		cell->set("\\" #_P4, sig4);                 \
 		add(cell);                                  \
 		return cell;                                \
 	} \
@@ -1098,9 +1098,9 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R
 	cell->parameters["\\A_WIDTH"] = sig_a.size();
 	cell->parameters["\\B_WIDTH"] = sig_b.size();
 	cell->parameters["\\Y_WIDTH"] = sig_y.size();
-	cell->connections_["\\A"] = sig_a;
+	cell->set("\\A", sig_a);
-	cell->connections_["\\B"] = sig_b;
+	cell->set("\\B", sig_b);
-	cell->connections_["\\Y"] = sig_y;
+	cell->set("\\Y", sig_y);
 	add(cell);
 	return cell;
 }
@@ -1113,8 +1113,8 @@ RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a,
 	cell->parameters["\\A_WIDTH"] = sig_a.size();
 	cell->parameters["\\Y_WIDTH"] = sig_y.size();
 	cell->parameters["\\OFFSET"] = offset;
-	cell->connections_["\\A"] = sig_a;
+	cell->set("\\A", sig_a);
-	cell->connections_["\\Y"] = sig_y;
+	cell->set("\\Y", sig_y);
 	add(cell);
 	return cell;
 }
@@ -1126,9 +1126,9 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a
 	cell->type = "$concat";
 	cell->parameters["\\A_WIDTH"] = sig_a.size();
 	cell->parameters["\\B_WIDTH"] = sig_b.size();
-	cell->connections_["\\A"] = sig_a;
+	cell->set("\\A", sig_a);
-	cell->connections_["\\B"] = sig_b;
+	cell->set("\\B", sig_b);
-	cell->connections_["\\Y"] = sig_y;
+	cell->set("\\Y", sig_y);
 	add(cell);
 	return cell;
 }
@@ -1140,8 +1140,8 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R
 	cell->type = "$lut";
 	cell->parameters["\\LUT"] = lut;
 	cell->parameters["\\WIDTH"] = sig_i.size();
-	cell->connections_["\\I"] = sig_i;
+	cell->set("\\I", sig_i);
-	cell->connections_["\\O"] = sig_o;
+	cell->set("\\O", sig_o);
 	add(cell);
 	return cell;
 }
@@ -1151,8 +1151,8 @@ RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a
 	RTLIL::Cell *cell = new RTLIL::Cell;
 	cell->name = name;
 	cell->type = "$assert";
-	cell->connections_["\\A"] = sig_a;
+	cell->set("\\A", sig_a);
-	cell->connections_["\\EN"] = sig_en;
+	cell->set("\\EN", sig_en);
 	add(cell);
 	return cell;
 }
@@ -1165,9 +1165,9 @@ RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set,
 	cell->parameters["\\SET_POLARITY"] = set_polarity;
 	cell->parameters["\\CLR_POLARITY"] = clr_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->connections_["\\SET"] = sig_set;
+	cell->set("\\SET", sig_set);
-	cell->connections_["\\CLR"] = sig_clr;
+	cell->set("\\CLR", sig_clr);
-	cell->connections_["\\Q"] = sig_q;
+	cell->set("\\Q", sig_q);
 	add(cell);
 	return cell;
 }
@@ -1179,9 +1179,9 @@ RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk,
 	cell->type = "$dff";
 	cell->parameters["\\CLK_POLARITY"] = clk_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->connections_["\\CLK"] = sig_clk;
+	cell->set("\\CLK", sig_clk);
-	cell->connections_["\\D"] = sig_d;
+	cell->set("\\D", sig_d);
-	cell->connections_["\\Q"] = sig_q;
+	cell->set("\\Q", sig_q);
 	add(cell);
 	return cell;
 }
@@ -1196,11 +1196,11 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_cl
 	cell->parameters["\\SET_POLARITY"] = set_polarity;
 	cell->parameters["\\CLR_POLARITY"] = clr_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->connections_["\\CLK"] = sig_clk;
+	cell->set("\\CLK", sig_clk);
-	cell->connections_["\\SET"] = sig_set;
+	cell->set("\\SET", sig_set);
-	cell->connections_["\\CLR"] = sig_clr;
+	cell->set("\\CLR", sig_clr);
-	cell->connections_["\\D"] = sig_d;
+	cell->set("\\D", sig_d);
-	cell->connections_["\\Q"] = sig_q;
+	cell->set("\\Q", sig_q);
 	add(cell);
 	return cell;
 }
@@ -1215,10 +1215,10 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk
 	cell->parameters["\\ARST_POLARITY"] = arst_polarity;
 	cell->parameters["\\ARST_VALUE"] = arst_value;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->connections_["\\CLK"] = sig_clk;
+	cell->set("\\CLK", sig_clk);
-	cell->connections_["\\ARST"] = sig_arst;
+	cell->set("\\ARST", sig_arst);
-	cell->connections_["\\D"] = sig_d;
+	cell->set("\\D", sig_d);
-	cell->connections_["\\Q"] = sig_q;
+	cell->set("\\Q", sig_q);
 	add(cell);
 	return cell;
 }
@@ -1230,9 +1230,9 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_e
 	cell->type = "$dlatch";
 	cell->parameters["\\EN_POLARITY"] = en_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->connections_["\\EN"] = sig_en;
+	cell->set("\\EN", sig_en);
-	cell->connections_["\\D"] = sig_d;
+	cell->set("\\D", sig_d);
-	cell->connections_["\\Q"] = sig_q;
+	cell->set("\\Q", sig_q);
 	add(cell);
 	return cell;
 }
@@ -1247,11 +1247,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig
 	cell->parameters["\\SET_POLARITY"] = set_polarity;
 	cell->parameters["\\CLR_POLARITY"] = clr_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->connections_["\\EN"] = sig_en;
+	cell->set("\\EN", sig_en);
-	cell->connections_["\\SET"] = sig_set;
+	cell->set("\\SET", sig_set);
-	cell->connections_["\\CLR"] = sig_clr;
+	cell->set("\\CLR", sig_clr);
-	cell->connections_["\\D"] = sig_d;
+	cell->set("\\D", sig_d);
-	cell->connections_["\\Q"] = sig_q;
+	cell->set("\\Q", sig_q);
 	add(cell);
 	return cell;
 }
@@ -1261,9 +1261,9 @@ RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_
 	RTLIL::Cell *cell = new RTLIL::Cell;
 	cell->name = name;
 	cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
-	cell->connections_["\\C"] = sig_clk;
+	cell->set("\\C", sig_clk);
-	cell->connections_["\\D"] = sig_d;
+	cell->set("\\D", sig_d);
-	cell->connections_["\\Q"] = sig_q;
+	cell->set("\\Q", sig_q);
 	add(cell);
 	return cell;
 }
@@ -1274,11 +1274,11 @@ RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec si
 	RTLIL::Cell *cell = new RTLIL::Cell;
 	cell->name = name;
 	cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
-	cell->connections_["\\C"] = sig_clk;
+	cell->set("\\C", sig_clk);
-	cell->connections_["\\S"] = sig_set;
+	cell->set("\\S", sig_set);
-	cell->connections_["\\R"] = sig_clr;
+	cell->set("\\R", sig_clr);
-	cell->connections_["\\D"] = sig_d;
+	cell->set("\\D", sig_d);
-	cell->connections_["\\Q"] = sig_q;
+	cell->set("\\Q", sig_q);
 	add(cell);
 	return cell;
 }
@@ -1289,10 +1289,10 @@ RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig
 	RTLIL::Cell *cell = new RTLIL::Cell;
 	cell->name = name;
 	cell->type = stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0');
-	cell->connections_["\\C"] = sig_clk;
+	cell->set("\\C", sig_clk);
-	cell->connections_["\\R"] = sig_arst;
+	cell->set("\\R", sig_arst);
-	cell->connections_["\\D"] = sig_d;
+	cell->set("\\D", sig_d);
-	cell->connections_["\\Q"] = sig_q;
+	cell->set("\\Q", sig_q);
 	add(cell);
 	return cell;
 }
@@ -1302,9 +1302,9 @@ RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec s
 	RTLIL::Cell *cell = new RTLIL::Cell;
 	cell->name = name;
 	cell->type = stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N');
-	cell->connections_["\\E"] = sig_en;
+	cell->set("\\E", sig_en);
-	cell->connections_["\\D"] = sig_d;
+	cell->set("\\D", sig_d);
-	cell->connections_["\\Q"] = sig_q;
+	cell->set("\\Q", sig_q);
 	add(cell);
 	return cell;
 }
@@ -1315,11 +1315,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec
 	RTLIL::Cell *cell = new RTLIL::Cell;
 	cell->name = name;
 	cell->type = stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
-	cell->connections_["\\E"] = sig_en;
+	cell->set("\\E", sig_en);
-	cell->connections_["\\S"] = sig_set;
+	cell->set("\\S", sig_set);
-	cell->connections_["\\R"] = sig_clr;
+	cell->set("\\R", sig_clr);
-	cell->connections_["\\D"] = sig_d;
+	cell->set("\\D", sig_d);
-	cell->connections_["\\Q"] = sig_q;
+	cell->set("\\Q", sig_q);
 	add(cell);
 	return cell;
 }

kernel/satgen.h

@@ -182,9 +182,9 @@ struct SatGen
 
 		if (model_undef && (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || is_arith_compare))
 		{
-			std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+			std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 			if (is_arith_compare)
 				extendSignalWidth(undef_a, undef_b, cell, true);
 			else
@@ -195,7 +195,7 @@ struct SatGen
 			int undef_y_bit = ez->OR(undef_any_a, undef_any_b);
 
 			if (cell->type == "$div" || cell->type == "$mod") {
-				std::vector<int> b = importSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> b = importSigSpec(cell->get("\\B"), timestep);
 				undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b)));
 			}
 
@@ -215,9 +215,9 @@ struct SatGen
 				cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" ||
 				cell->type == "$add" || cell->type == "$sub")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
 			extendSignalWidth(a, b, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -237,9 +237,9 @@ struct SatGen
 
 			if (model_undef && !arith_undef_handled)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 				extendSignalWidth(undef_a, undef_b, undef_y, cell, false);
 
 				if (cell->type == "$and" || cell->type == "$_AND_") {
@@ -265,7 +265,7 @@ struct SatGen
 			}
 			else if (model_undef)
 			{
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 				undefGating(y, yy, undef_y);
 			}
 			return true;
@@ -273,16 +273,16 @@ struct SatGen
 
 		if (cell->type == "$_INV_" || cell->type == "$not")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
 			extendSignalWidthUnary(a, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 			ez->assume(ez->vec_eq(ez->vec_not(a), yy));
 
 			if (model_undef) {
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 				extendSignalWidthUnary(undef_a, undef_y, cell, true);
 				ez->assume(ez->vec_eq(undef_a, undef_y));
 				undefGating(y, yy, undef_y);
@@ -292,20 +292,20 @@ struct SatGen
 
 		if (cell->type == "$_MUX_" || cell->type == "$mux")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> s = importDefSigSpec(cell->connections_.at("\\S"), timestep);
+			std::vector<int> s = importDefSigSpec(cell->get("\\S"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 			ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy));
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-				std::vector<int> undef_s = importUndefSigSpec(cell->connections_.at("\\S"), timestep);
+				std::vector<int> undef_s = importUndefSigSpec(cell->get("\\S"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 
 				std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));
 				std::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));
@@ -318,10 +318,10 @@ struct SatGen
 
 		if (cell->type == "$pmux" || cell->type == "$safe_pmux")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> s = importDefSigSpec(cell->connections_.at("\\S"), timestep);
+			std::vector<int> s = importDefSigSpec(cell->get("\\S"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
@@ -336,10 +336,10 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-				std::vector<int> undef_s = importUndefSigSpec(cell->connections_.at("\\S"), timestep);
+				std::vector<int> undef_s = importUndefSigSpec(cell->get("\\S"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 
 				int maybe_one_hot = ez->FALSE;
 				int maybe_many_hot = ez->FALSE;
@@ -387,8 +387,8 @@ struct SatGen
 
 		if (cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
 			extendSignalWidthUnary(a, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -402,8 +402,8 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 				extendSignalWidthUnary(undef_a, undef_y, cell, cell->type != "$bu0");
 
 				if (cell->type == "$pos" || cell->type == "$bu0") {
@@ -422,8 +422,8 @@ struct SatGen
 		if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
 				cell->type == "$reduce_xnor" || cell->type == "$reduce_bool" || cell->type == "$logic_not")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
@@ -442,8 +442,8 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 				int aX = ez->expression(ezSAT::OpOr, undef_a);
 
 				if (cell->type == "$reduce_and") {
@@ -469,12 +469,12 @@ struct SatGen
 
 		if (cell->type == "$logic_and" || cell->type == "$logic_or")
 		{
-			std::vector<int> vec_a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> vec_a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> vec_b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> vec_b = importDefSigSpec(cell->get("\\B"), timestep);
 
 			int a = ez->expression(ez->OpOr, vec_a);
 			int b = ez->expression(ez->OpOr, vec_b);
-			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
@@ -487,9 +487,9 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 
 				int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a)));
 				int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b)));
@@ -516,16 +516,16 @@ struct SatGen
 		if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt")
 		{
 			bool is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool();
-			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
 			extendSignalWidth(a, b, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
 			if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) {
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
 				extendSignalWidth(undef_a, undef_b, cell, true);
 				a = ez->vec_or(a, undef_a);
 				b = ez->vec_or(b, undef_b);
@@ -548,9 +548,9 @@ struct SatGen
 
 			if (model_undef && (cell->type == "$eqx" || cell->type == "$nex"))
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 				extendSignalWidth(undef_a, undef_b, cell, true);
 
 				if (cell->type == "$eqx")
@@ -565,9 +565,9 @@ struct SatGen
 			}
 			else if (model_undef && (cell->type == "$eq" || cell->type == "$ne"))
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 				extendSignalWidth(undef_a, undef_b, cell, true);
 
 				int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
@@ -589,7 +589,7 @@ struct SatGen
 			else
 			{
 				if (model_undef) {
-					std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+					std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 					undefGating(y, yy, undef_y);
 				}
 				log_assert(!model_undef || arith_undef_handled);
@@ -599,9 +599,9 @@ struct SatGen
 
 		if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
 
 			char shift_left = cell->type == "$shl" || cell->type == "$sshl";
 			bool sign_extend = cell->type == "$sshr" && cell->parameters["\\A_SIGNED"].as_bool();
@@ -627,9 +627,9 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 
 				while (undef_y.size() < undef_a.size())
 					undef_y.push_back(ez->literal());
@@ -657,9 +657,9 @@ struct SatGen
 
 		if (cell->type == "$mul")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
 			extendSignalWidth(a, b, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -676,7 +676,7 @@ struct SatGen
 
 			if (model_undef) {
 				log_assert(arith_undef_handled);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 				undefGating(y, yy, undef_y);
 			}
 			return true;
@@ -684,9 +684,9 @@ struct SatGen
 
 		if (cell->type == "$div" || cell->type == "$mod")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
 			extendSignalWidth(a, b, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -740,11 +740,11 @@ struct SatGen
 						only_first_one.at(0) = ez->TRUE;
 						div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones);
 					} else {
-						div_zero_result.insert(div_zero_result.end(), cell->connections_.at("\\A").size(), ez->TRUE);
+						div_zero_result.insert(div_zero_result.end(), cell->get("\\A").size(), ez->TRUE);
 						div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE);
 					}
 				} else {
-					int copy_a_bits = std::min(cell->connections_.at("\\A").size(), cell->connections_.at("\\B").size());
+					int copy_a_bits = std::min(cell->get("\\A").size(), cell->get("\\B").size());
 					div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
 					if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
 						div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
@@ -756,7 +756,7 @@ struct SatGen
 
 			if (model_undef) {
 				log_assert(arith_undef_handled);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
 				undefGating(y, yy, undef_y);
 			}
 			return true;
@@ -764,17 +764,17 @@ struct SatGen
 
 		if (cell->type == "$slice")
 		{
-			RTLIL::SigSpec a = cell->connections_.at("\\A");
+			RTLIL::SigSpec a = cell->get("\\A");
-			RTLIL::SigSpec y = cell->connections_.at("\\Y");
+			RTLIL::SigSpec y = cell->get("\\Y");
 			ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.size()), y, timestep));
 			return true;
 		}
 
 		if (cell->type == "$concat")
 		{
-			RTLIL::SigSpec a = cell->connections_.at("\\A");
+			RTLIL::SigSpec a = cell->get("\\A");
-			RTLIL::SigSpec b = cell->connections_.at("\\B");
+			RTLIL::SigSpec b = cell->get("\\B");
-			RTLIL::SigSpec y = cell->connections_.at("\\Y");
+			RTLIL::SigSpec y = cell->get("\\Y");
 
 			RTLIL::SigSpec ab = a;
 			ab.append(b);
@@ -787,20 +787,20 @@ struct SatGen
 		{
 			if (timestep == 1)
 			{
-				initial_state.add((*sigmap)(cell->connections_.at("\\Q")));
+				initial_state.add((*sigmap)(cell->get("\\Q")));
 			}
 			else
 			{
-				std::vector<int> d = importDefSigSpec(cell->connections_.at("\\D"), timestep-1);
+				std::vector<int> d = importDefSigSpec(cell->get("\\D"), timestep-1);
-				std::vector<int> q = importDefSigSpec(cell->connections_.at("\\Q"), timestep);
+				std::vector<int> q = importDefSigSpec(cell->get("\\Q"), timestep);
 
 				std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q;
 				ez->assume(ez->vec_eq(d, qq));
 
 				if (model_undef)
 				{
-					std::vector<int> undef_d = importUndefSigSpec(cell->connections_.at("\\D"), timestep-1);
+					std::vector<int> undef_d = importUndefSigSpec(cell->get("\\D"), timestep-1);
-					std::vector<int> undef_q = importUndefSigSpec(cell->connections_.at("\\Q"), timestep);
+					std::vector<int> undef_q = importUndefSigSpec(cell->get("\\Q"), timestep);
 
 					ez->assume(ez->vec_eq(undef_d, undef_q));
 					undefGating(q, qq, undef_q);
@@ -812,8 +812,8 @@ struct SatGen
 		if (cell->type == "$assert")
 		{
 			std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
-			asserts_a[pf].append((*sigmap)(cell->connections_.at("\\A")));
+			asserts_a[pf].append((*sigmap)(cell->get("\\A")));
-			asserts_en[pf].append((*sigmap)(cell->connections_.at("\\EN")));
+			asserts_en[pf].append((*sigmap)(cell->get("\\EN")));
 			return true;
 		}
 

kernel/sigtools.h

@@ -269,7 +269,7 @@ struct SigMap
 	void set(RTLIL::Module *module)
 	{
 		clear();
-		for (auto &it : module->connections_)
+		for (auto &it : module->connections())
 			add(it.first, it.second);
 	}
 

manual/CHAPTER_Prog/stubnets.cc

@@ -30,7 +30,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 
 	// For all ports on all cells
 	for (auto &cell_iter : module->cells)
-	for (auto &conn : cell_iter.second->connections_)
+	for (auto &conn : cell_iter.second->connections())
 	{
 		// Get the signals on the port
 		// (use sigmap to get a uniqe signal name)

passes/abc/abc.cc

@@ -111,11 +111,11 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
 	{
 		if (clk_polarity != (cell->type == "$_DFF_P_"))
 			return;
-		if (clk_sig != assign_map(cell->connections_["\\C"]))
+		if (clk_sig != assign_map(cell->get("\\C")))
 			return;
 
-		RTLIL::SigSpec sig_d = cell->connections_["\\D"];
+		RTLIL::SigSpec sig_d = cell->get("\\D");
-		RTLIL::SigSpec sig_q = cell->connections_["\\Q"];
+		RTLIL::SigSpec sig_q = cell->get("\\Q");
 
 		if (keepff)
 			for (auto &c : sig_q.chunks())
@@ -133,8 +133,8 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
 
 	if (cell->type == "$_INV_")
 	{
-		RTLIL::SigSpec sig_a = cell->connections_["\\A"];
+		RTLIL::SigSpec sig_a = cell->get("\\A");
-		RTLIL::SigSpec sig_y = cell->connections_["\\Y"];
+		RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 		assign_map.apply(sig_a);
 		assign_map.apply(sig_y);
@@ -147,9 +147,9 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
 
 	if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_")
 	{
-		RTLIL::SigSpec sig_a = cell->connections_["\\A"];
+		RTLIL::SigSpec sig_a = cell->get("\\A");
-		RTLIL::SigSpec sig_b = cell->connections_["\\B"];
+		RTLIL::SigSpec sig_b = cell->get("\\B");
-		RTLIL::SigSpec sig_y = cell->connections_["\\Y"];
+		RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 		assign_map.apply(sig_a);
 		assign_map.apply(sig_b);
@@ -173,10 +173,10 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
 
 	if (cell->type == "$_MUX_")
 	{
-		RTLIL::SigSpec sig_a = cell->connections_["\\A"];
+		RTLIL::SigSpec sig_a = cell->get("\\A");
-		RTLIL::SigSpec sig_b = cell->connections_["\\B"];
+		RTLIL::SigSpec sig_b = cell->get("\\B");
-		RTLIL::SigSpec sig_s = cell->connections_["\\S"];
+		RTLIL::SigSpec sig_s = cell->get("\\S");
-		RTLIL::SigSpec sig_y = cell->connections_["\\Y"];
+		RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 		assign_map.apply(sig_a);
 		assign_map.apply(sig_b);
@@ -347,7 +347,7 @@ static void handle_loops()
 			}
 			edges[id1].swap(edges[id3]);
 
-			module->connections_.push_back(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit));
+			module->connect(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit));
 			dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
 		}
 	}
@@ -470,7 +470,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 			if (cell->type != "$_DFF_N_" && cell->type != "$_DFF_P_")
 				continue;
 
-			std::pair<bool, RTLIL::SigSpec> key(cell->type == "$_DFF_P_", assign_map(cell->connections_.at("\\C")));
+			std::pair<bool, RTLIL::SigSpec> key(cell->type == "$_DFF_P_", assign_map(cell->get("\\C")));
 			if (++dff_counters[key] > best_dff_counter) {
 				best_dff_counter = dff_counters[key];
 				clk_polarity = key.first;
@@ -503,7 +503,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 	}
 
 	for (auto &cell_it : module->cells)
-	for (auto &port_it : cell_it.second->connections_)
+	for (auto &port_it : cell_it.second->connections())
 		mark_port(port_it.second);
 	
 	handle_loops();
@@ -705,48 +705,48 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 				cell_stats[RTLIL::unescape_id(c->type)]++;
 				if (c->type == "\\ZERO" || c->type == "\\ONE") {
 					RTLIL::SigSig conn;
-					conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]);
+					conn.first = RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]);
 					conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1);
-					module->connections_.push_back(conn);
+					module->connect(conn);
 					continue;
 				}
 				if (c->type == "\\BUF") {
 					RTLIL::SigSig conn;
-					conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]);
+					conn.first = RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]);
-					conn.second = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]);
+					conn.second = RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)]);
-					module->connections_.push_back(conn);
+					module->connect(conn);
 					continue;
 				}
 				if (c->type == "\\INV") {
 					RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_INV_");
-					cell->connections_["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]);
+					cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)]));
-					cell->connections_["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]);
+					cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]));
 					design->select(module, cell);
 					continue;
 				}
 				if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") {
 					RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
-					cell->connections_["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]);
+					cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)]));
-					cell->connections_["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\B"].as_wire()->name)]);
+					cell->set("\\B", RTLIL::SigSpec(module->wires[remap_name(c->get("\\B").as_wire()->name)]));
-					cell->connections_["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]);
+					cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]));
 					design->select(module, cell);
 					continue;
 				}
 				if (c->type == "\\MUX") {
 					RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_");
-					cell->connections_["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\A"].as_wire()->name)]);
+					cell->set("\\A", RTLIL::SigSpec(module->wires[remap_name(c->get("\\A").as_wire()->name)]));
-					cell->connections_["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\B"].as_wire()->name)]);
+					cell->set("\\B", RTLIL::SigSpec(module->wires[remap_name(c->get("\\B").as_wire()->name)]));
-					cell->connections_["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\S"].as_wire()->name)]);
+					cell->set("\\S", RTLIL::SigSpec(module->wires[remap_name(c->get("\\S").as_wire()->name)]));
-					cell->connections_["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Y"].as_wire()->name)]);
+					cell->set("\\Y", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Y").as_wire()->name)]));
 					design->select(module, cell);
 					continue;
 				}
 				if (c->type == "\\DFF") {
 					log_assert(clk_sig.size() == 1);
 					RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
-					cell->connections_["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\D"].as_wire()->name)]);
+					cell->set("\\D", RTLIL::SigSpec(module->wires[remap_name(c->get("\\D").as_wire()->name)]));
-					cell->connections_["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Q"].as_wire()->name)]);
+					cell->set("\\Q", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Q").as_wire()->name)]));
-					cell->connections_["\\C"] = clk_sig;
+					cell->set("\\C", clk_sig);
 					design->select(module, cell);
 					continue;
 				}
@@ -761,23 +761,23 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 				cell_stats[RTLIL::unescape_id(c->type)]++;
 				if (c->type == "\\_const0_" || c->type == "\\_const1_") {
 					RTLIL::SigSig conn;
-					conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections_.begin()->second.as_wire()->name)]);
+					conn.first = RTLIL::SigSpec(module->wires[remap_name(c->connections().begin()->second.as_wire()->name)]);
 					conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1);
-					module->connections_.push_back(conn);
+					module->connect(conn);
 					continue;
 				}
 				if (c->type == "\\_dff_") {
 					log_assert(clk_sig.size() == 1);
 					RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
-					cell->connections_["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\D"].as_wire()->name)]);
+					cell->set("\\D", RTLIL::SigSpec(module->wires[remap_name(c->get("\\D").as_wire()->name)]));
-					cell->connections_["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections_["\\Q"].as_wire()->name)]);
+					cell->set("\\Q", RTLIL::SigSpec(module->wires[remap_name(c->get("\\Q").as_wire()->name)]));
-					cell->connections_["\\C"] = clk_sig;
+					cell->set("\\C", clk_sig);
 					design->select(module, cell);
 					continue;
 				}
 				RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
 				cell->parameters = c->parameters;
-				for (auto &conn : c->connections_) {
+				for (auto &conn : c->connections()) {
 					RTLIL::SigSpec newsig;
 					for (auto &c : conn.second.chunks()) {
 						if (c.width == 0)
@@ -785,18 +785,18 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 						assert(c.width == 1);
 						newsig.append(module->wires[remap_name(c.wire->name)]);
 					}
-					cell->connections_[conn.first] = newsig;
+					cell->set(conn.first, newsig);
 				}
 				design->select(module, cell);
 			}
 		}
 
-		for (auto conn : mapped_mod->connections_) {
+		for (auto conn : mapped_mod->connections()) {
 			if (!conn.first.is_fully_const())
 				conn.first = RTLIL::SigSpec(module->wires[remap_name(conn.first.as_wire()->name)]);
 			if (!conn.second.is_fully_const())
 				conn.second = RTLIL::SigSpec(module->wires[remap_name(conn.second.as_wire()->name)]);
-			module->connections_.push_back(conn);
+			module->connect(conn);
 		}
 
 		for (auto &it : cell_stats)
@@ -816,7 +816,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 					conn.second = si.bit;
 					in_wires++;
 				}
-				module->connections_.push_back(conn);
+				module->connect(conn);
 			}
 		log("ABC RESULTS:        internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
 		log("ABC RESULTS:           input signals: %8d\n", in_wires);

passes/abc/blifparse.cc

@@ -128,8 +128,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 				}
 
 				RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name);
-				cell->connections_["\\D"] = module->wires.at(RTLIL::escape_id(d));
+				cell->set("\\D", module->wires.at(RTLIL::escape_id(d)));
-				cell->connections_["\\Q"] = module->wires.at(RTLIL::escape_id(q));
+				cell->set("\\Q", module->wires.at(RTLIL::escape_id(q)));
 				continue;
 			}
 
@@ -148,7 +148,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 					*(q++) = 0;
 					if (module->wires.count(RTLIL::escape_id(q)) == 0)
 						module->addWire(RTLIL::escape_id(q));
-					cell->connections_[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q));
+					cell->set(RTLIL::escape_id(p), module->wires.at(RTLIL::escape_id(q)));
 				}
 				continue;
 			}
@@ -199,15 +199,15 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 				finished_parsing_constval:
 					if (state == RTLIL::State::Sa)
 						state = RTLIL::State::S1;
-					module->connections_.push_back(RTLIL::SigSig(output_sig, state));
+					module->connect(RTLIL::SigSig(output_sig, state));
 					goto continue_without_read;
 				}
 
 				RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
 				cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
 				cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
-				cell->connections_["\\I"] = input_sig;
+				cell->set("\\I", input_sig);
-				cell->connections_["\\O"] = output_sig;
+				cell->set("\\O", output_sig);
 				lutptr = &cell->parameters.at("\\LUT");
 				lut_default_state = RTLIL::State::Sx;
 				continue;

passes/cmds/add.cc

@@ -75,10 +75,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
 			continue;
 		if (mod->get_bool_attribute("\\blackbox"))
 			continue;
-		if (it.second->connections_.count(name) > 0)
+		if (it.second->connections().count(name) > 0)
 			continue;
 
-		it.second->connections_[name] = wire;
+		it.second->set(name, wire);
 		log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
 	}
 }

passes/cmds/connect.cc

@@ -123,7 +123,7 @@ struct ConnectPass : public Pass {
 
 		SigMap sigmap;
 		if (!flag_nomap)
-			for (auto &it : module->connections_) {
+			for (auto &it : module->connections()) {
 				std::vector<RTLIL::SigBit> lhs = it.first.to_sigbit_vector();
 				std::vector<RTLIL::SigBit> rhs = it.first.to_sigbit_vector();
 				for (size_t i = 0; i < lhs.size(); i++)
@@ -148,7 +148,7 @@ struct ConnectPass : public Pass {
 			if (!flag_nounset)
 				unset_drivers(design, module, sigmap, sig_lhs);
 
-			module->connections_.push_back(RTLIL::SigSig(sig_lhs, sig_rhs));
+			module->connect(RTLIL::SigSig(sig_lhs, sig_rhs));
 		}
 		else
 		if (!unset_expr.empty())
@@ -176,7 +176,7 @@ struct ConnectPass : public Pass {
 			if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
 				log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
 
-			module->cells.at(RTLIL::escape_id(port_cell))->connections_[RTLIL::escape_id(port_port)] = sigmap(sig);
+			module->cells.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig));
 		}
 		else
 			log_cmd_error("Expected -set, -unset, or -port.\n");

passes/cmds/connwrappers.cc

@@ -74,7 +74,7 @@ struct ConnwrappersWorker
 			if (!decl_celltypes.count(cell->type))
 				continue;
 
-			for (auto &conn : cell->connections_)
+			for (auto &conn : cell->connections())
 			{
 				std::pair<std::string, std::string> key(cell->type, conn.first);
 

passes/cmds/scatter.cc

@@ -58,10 +58,10 @@ struct ScatterPass : public Pass {
 
 				if (ct.cell_output(c.second->type, p.first)) {
 					RTLIL::SigSig sigsig(p.second, wire);
-					mod_it.second->connections_.push_back(sigsig);
+					mod_it.second->connect(sigsig);
 				} else {
 					RTLIL::SigSig sigsig(wire, p.second);
-					mod_it.second->connections_.push_back(sigsig);
+					mod_it.second->connect(sigsig);
 				}
 
 				p.second = wire;

passes/cmds/scc.cc

@@ -132,7 +132,7 @@ struct SccWorker
 
 			RTLIL::SigSpec inputSignals, outputSignals;
 
-			for (auto &conn : cell->connections_)
+			for (auto &conn : cell->connections())
 			{
 				bool isInput = true, isOutput = true;
 

passes/cmds/select.cc

@@ -380,7 +380,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 			if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0)
 				selected_wires.insert(it.second);
 
-		for (auto &conn : mod->connections_)
+		for (auto &conn : mod->connections())
 		{
 			std::vector<RTLIL::SigBit> conn_lhs = conn.first.to_sigbit_vector();
 			std::vector<RTLIL::SigBit> conn_rhs = conn.second.to_sigbit_vector();
@@ -396,7 +396,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 		}
 
 		for (auto &cell : mod->cells)
-		for (auto &conn : cell.second->connections_)
+		for (auto &conn : cell.second->connections())
 		{
 			char last_mode = '-';
 			for (auto &rule : rules) {

passes/cmds/setundef.cc

@@ -135,7 +135,7 @@ struct SetundefPass : public Pass {
 
 				CellTypes ct(design);
 				for (auto &it : module->cells)
-				for (auto &conn : it.second->connections_)
+				for (auto &conn : it.second->connections())
 					if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
 						undriven_signals.del(sigmap(conn.second));
 
@@ -144,7 +144,7 @@ struct SetundefPass : public Pass {
 					RTLIL::SigSpec bits;
 					for (int i = 0; i < c.width; i++)
 						bits.append(worker.next_bit());
-					module->connections_.push_back(RTLIL::SigSig(c, bits));
+					module->connect(RTLIL::SigSig(c, bits));
 				}
 			}
 

passes/cmds/show.cc

@@ -87,17 +87,17 @@ struct ShowWorker
 		return defaultColor;
 	}
 
-	std::string nextColor(RTLIL::SigSig &conn, std::string defaultColor)
+	std::string nextColor(const RTLIL::SigSig &conn, std::string defaultColor)
 	{
 		return nextColor(conn.first, nextColor(conn.second, defaultColor));
 	}
 
-	std::string nextColor(RTLIL::SigSpec &sig)
+	std::string nextColor(const RTLIL::SigSpec &sig)
 	{
 		return nextColor(sig, nextColor());
 	}
 
-	std::string nextColor(RTLIL::SigSig &conn)
+	std::string nextColor(const RTLIL::SigSig &conn)
 	{
 		return nextColor(conn, nextColor());
 	}
@@ -344,7 +344,7 @@ struct ShowWorker
 
 			std::vector<RTLIL::IdString> in_ports, out_ports;
 
-			for (auto &conn : it.second->connections_) {
+			for (auto &conn : it.second->connections()) {
 				if (!ct.cell_output(it.second->type, conn.first))
 					in_ports.push_back(conn.first);
 				else
@@ -368,7 +368,7 @@ struct ShowWorker
 			label_string += "}}";
 
 			std::string code;
-			for (auto &conn : it.second->connections_) {
+			for (auto &conn : it.second->connections()) {
 				code += gen_portbox(stringf("c%d:p%d", id2num(it.first), id2num(conn.first)),
 						conn.second, ct.cell_output(it.second->type, conn.first));
 			}
@@ -421,7 +421,7 @@ struct ShowWorker
 			fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name), proc_src.c_str());
 		}
 
-		for (auto &conn : module->connections_)
+		for (auto &conn : module->connections())
 		{
 			bool found_lhs_wire = false;
 			for (auto &c : conn.first.chunks()) {
@@ -516,7 +516,7 @@ struct ShowWorker
 					log("Skipping blackbox module %s.\n", id2cstr(module->name));
 					continue;
 				} else
-				if (module->cells.empty() && module->connections_.empty() && module->processes.empty()) {
+				if (module->cells.empty() && module->connections().empty() && module->processes.empty()) {
 					log("Skipping empty module %s.\n", id2cstr(module->name));
 					continue;
 				} else
@@ -695,7 +695,7 @@ struct ShowPass : public Pass {
 			for (auto &mod_it : design->modules) {
 				if (mod_it.second->get_bool_attribute("\\blackbox"))
 					continue;
-				if (mod_it.second->cells.empty() && mod_it.second->connections_.empty())
+				if (mod_it.second->cells.empty() && mod_it.second->connections().empty())
 					continue;
 				if (design->selected_module(mod_it.first))
 					modcount++;

passes/cmds/splice.cc

@@ -74,9 +74,9 @@ struct SpliceWorker
 			cell->parameters["\\OFFSET"] = offset;
 			cell->parameters["\\A_WIDTH"] = sig_a.size();
 			cell->parameters["\\Y_WIDTH"] = sig.size();
-			cell->connections_["\\A"] = sig_a;
+			cell->set("\\A", sig_a);
-			cell->connections_["\\Y"] = module->addWire(NEW_ID, sig.size());
+			cell->set("\\Y", module->addWire(NEW_ID, sig.size()));
-			new_sig = cell->connections_["\\Y"];
+			new_sig = cell->get("\\Y");
 		}
 
 		sliced_signals_cache[sig] = new_sig;
@@ -130,10 +130,10 @@ struct SpliceWorker
 			RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
 			cell->parameters["\\A_WIDTH"] = new_sig.size();
 			cell->parameters["\\B_WIDTH"] = sig2.size();
-			cell->connections_["\\A"] = new_sig;
+			cell->set("\\A", new_sig);
-			cell->connections_["\\B"] = sig2;
+			cell->set("\\B", sig2);
-			cell->connections_["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size());
+			cell->set("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size()));
-			new_sig = cell->connections_["\\Y"];
+			new_sig = cell->get("\\Y");
 		}
 
 		spliced_signals_cache[sig] = new_sig;
@@ -159,7 +159,7 @@ struct SpliceWorker
 			}
 
 		for (auto &it : module->cells)
-		for (auto &conn : it.second->connections_)
+		for (auto &conn : it.second->connections())
 			if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) {
 				RTLIL::SigSpec sig = sigmap(conn.second);
 				driven_chunks.insert(sig);
@@ -232,7 +232,7 @@ struct SpliceWorker
 			it.first->port_output = false;
 			module->add(it.first);
 			module->add(new_port);
-			module->connections_.push_back(RTLIL::SigSig(new_port, it.second));
+			module->connect(RTLIL::SigSig(new_port, it.second));
 		}
 	}
 };

passes/cmds/splitnets.cc

@@ -134,7 +134,7 @@ struct SplitnetsPass : public Pass {
 				std::map<RTLIL::Wire*, std::set<int>> split_wires_at;
 
 				for (auto &c : module->cells)
-				for (auto &p : c.second->connections_)
+				for (auto &p : c.second->connections())
 				{
 					if (!ct.cell_known(c.second->type))
 						continue;

passes/fsm/fsm_detect.cc

@@ -52,8 +52,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig
 	for (auto &cellport : cellport_list) {
 		if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y")
 			return false;
-		RTLIL::SigSpec sig_a = assign_map(cellport.first->connections_["\\A"]);
+		RTLIL::SigSpec sig_a = assign_map(cellport.first->get("\\A"));
-		RTLIL::SigSpec sig_b = assign_map(cellport.first->connections_["\\B"]);
+		RTLIL::SigSpec sig_b = assign_map(cellport.first->get("\\B"));
 		if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor))
 			return false;
 		for (int i = 0; i < sig_b.size(); i += sig_a.size())
@@ -80,14 +80,14 @@ static bool check_state_users(RTLIL::SigSpec sig)
 			continue;
 		if (cellport.second != "\\A" && cellport.second != "\\B")
 			return false;
-		if (cell->connections_.count("\\A") == 0 || cell->connections_.count("\\B") == 0 || cell->connections_.count("\\Y") == 0)
+		if (cell->connections().count("\\A") == 0 || cell->connections().count("\\B") == 0 || cell->connections().count("\\Y") == 0)
 			return false;
-		for (auto &port_it : cell->connections_)
+		for (auto &port_it : cell->connections())
 			if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y")
 				return false;
-		if (assign_map(cell->connections_["\\A"]) == sig && cell->connections_["\\B"].is_fully_const())
+		if (assign_map(cell->get("\\A")) == sig && cell->get("\\B").is_fully_const())
 			continue;
-		if (assign_map(cell->connections_["\\B"]) == sig && cell->connections_["\\A"].is_fully_const())
+		if (assign_map(cell->get("\\B")) == sig && cell->get("\\A").is_fully_const())
 			continue;
 		return false;
 	}
@@ -109,8 +109,8 @@ static void detect_fsm(RTLIL::Wire *wire)
 			continue;
 		muxtree_cells.clear();
 		SigPool recursion_monitor;
-		RTLIL::SigSpec sig_q = assign_map(cellport.first->connections_["\\Q"]);
+		RTLIL::SigSpec sig_q = assign_map(cellport.first->get("\\Q"));
-		RTLIL::SigSpec sig_d = assign_map(cellport.first->connections_["\\D"]);
+		RTLIL::SigSpec sig_d = assign_map(cellport.first->get("\\D"));
 		if (sig_q == RTLIL::SigSpec(wire) && check_state_mux_tree(sig_q, sig_d, recursion_monitor) && check_state_users(sig_q)) {
 			log("Found FSM state register %s in module %s.\n", wire->name.c_str(), module->name.c_str());
 			wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto");
@@ -160,7 +160,7 @@ struct FsmDetectPass : public Pass {
 			sig2user.clear();
 			sig_at_port.clear();
 			for (auto &cell_it : module->cells)
-				for (auto &conn_it : cell_it.second->connections_) {
+				for (auto &conn_it : cell_it.second->connections()) {
 					if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
 						RTLIL::SigSpec sig = conn_it.second;
 						assign_map.apply(sig);

passes/fsm/fsm_expand.cc

@@ -43,34 +43,34 @@ struct FsmExpand
 	bool is_cell_merge_candidate(RTLIL::Cell *cell)
 	{
 		if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
-			if (cell->connections_.at("\\A").size() < 2)
+			if (cell->get("\\A").size() < 2)
 				return true;
 
 		RTLIL::SigSpec new_signals;
-		if (cell->connections_.count("\\A") > 0)
+		if (cell->connections().count("\\A") > 0)
-			new_signals.append(assign_map(cell->connections_["\\A"]));
+			new_signals.append(assign_map(cell->get("\\A")));
-		if (cell->connections_.count("\\B") > 0)
+		if (cell->connections().count("\\B") > 0)
-			new_signals.append(assign_map(cell->connections_["\\B"]));
+			new_signals.append(assign_map(cell->get("\\B")));
-		if (cell->connections_.count("\\S") > 0)
+		if (cell->connections().count("\\S") > 0)
-			new_signals.append(assign_map(cell->connections_["\\S"]));
+			new_signals.append(assign_map(cell->get("\\S")));
-		if (cell->connections_.count("\\Y") > 0)
+		if (cell->connections().count("\\Y") > 0)
-			new_signals.append(assign_map(cell->connections_["\\Y"]));
+			new_signals.append(assign_map(cell->get("\\Y")));
 
 		new_signals.sort_and_unify();
 		new_signals.remove_const();
 
-		new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_IN"]));
+		new_signals.remove(assign_map(fsm_cell->get("\\CTRL_IN")));
-		new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_OUT"]));
+		new_signals.remove(assign_map(fsm_cell->get("\\CTRL_OUT")));
 
 		if (new_signals.size() > 3)
 			return false;
 
-		if (cell->connections_.count("\\Y") > 0) {
+		if (cell->connections().count("\\Y") > 0) {
-			new_signals.append(assign_map(cell->connections_["\\Y"]));
+			new_signals.append(assign_map(cell->get("\\Y")));
 			new_signals.sort_and_unify();
 			new_signals.remove_const();
-			new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_IN"]));
+			new_signals.remove(assign_map(fsm_cell->get("\\CTRL_IN")));
-			new_signals.remove(assign_map(fsm_cell->connections_["\\CTRL_OUT"]));
+			new_signals.remove(assign_map(fsm_cell->get("\\CTRL_OUT")));
 		}
 
 		if (new_signals.size() > 2)
@@ -83,10 +83,10 @@ struct FsmExpand
 	{
 		std::vector<RTLIL::Cell*> cell_list;
 
-		for (auto c : sig2driver.find(assign_map(fsm_cell->connections_["\\CTRL_IN"])))
+		for (auto c : sig2driver.find(assign_map(fsm_cell->get("\\CTRL_IN"))))
 			cell_list.push_back(c);
 
-		for (auto c : sig2user.find(assign_map(fsm_cell->connections_["\\CTRL_OUT"])))
+		for (auto c : sig2user.find(assign_map(fsm_cell->get("\\CTRL_OUT"))))
 			cell_list.push_back(c);
 
 		current_set.clear();
@@ -94,7 +94,7 @@ struct FsmExpand
 		{
 			if (merged_set.count(c) > 0 || current_set.count(c) > 0 || no_candidate_set.count(c) > 0)
 				continue;
-			for (auto &p : c->connections_) {
+			for (auto &p : c->connections()) {
 				if (p.first != "\\A" && p.first != "\\B" && p.first != "\\S" && p.first != "\\Y")
 					goto next_cell;
 			}
@@ -135,7 +135,7 @@ struct FsmExpand
 
 		RTLIL::SigSpec input_sig, output_sig;
 
-		for (auto &p : cell->connections_)
+		for (auto &p : cell->connections())
 			if (ct.cell_output(cell->type, p.first))
 				output_sig.append(assign_map(p.second));
 			else
@@ -148,12 +148,12 @@ struct FsmExpand
 		for (int i = 0; i < (1 << input_sig.size()); i++) {
 			RTLIL::Const in_val(i, input_sig.size());
 			RTLIL::SigSpec A, B, S;
-			if (cell->connections_.count("\\A") > 0)
+			if (cell->connections().count("\\A") > 0)
-				A = assign_map(cell->connections_["\\A"]);
+				A = assign_map(cell->get("\\A"));
-			if (cell->connections_.count("\\B") > 0)
+			if (cell->connections().count("\\B") > 0)
-				B = assign_map(cell->connections_["\\B"]);
+				B = assign_map(cell->get("\\B"));
-			if (cell->connections_.count("\\S") > 0)
+			if (cell->connections().count("\\S") > 0)
-				S = assign_map(cell->connections_["\\S"]);
+				S = assign_map(cell->get("\\S"));
 			A.replace(input_sig, RTLIL::SigSpec(in_val));
 			B.replace(input_sig, RTLIL::SigSpec(in_val));
 			S.replace(input_sig, RTLIL::SigSpec(in_val));
@@ -167,10 +167,14 @@ struct FsmExpand
 		fsm_data.copy_from_cell(fsm_cell);
 
 		fsm_data.num_inputs += input_sig.size();
-		fsm_cell->connections_["\\CTRL_IN"].append(input_sig);
+		RTLIL::SigSpec new_ctrl_in = fsm_cell->get("\\CTRL_IN");
+		new_ctrl_in.append(input_sig);
+		fsm_cell->set("\\CTRL_IN", new_ctrl_in);
 
 		fsm_data.num_outputs += output_sig.size();
-		fsm_cell->connections_["\\CTRL_OUT"].append(output_sig);
+		RTLIL::SigSpec new_ctrl_out = fsm_cell->get("\\CTRL_OUT");
+		new_ctrl_out.append(output_sig);
+		fsm_cell->set("\\CTRL_OUT", new_ctrl_out);
 
 		std::vector<FsmData::transition_t> new_transition_table;
 		for (auto &tr : fsm_data.transition_table) {
@@ -204,7 +208,7 @@ struct FsmExpand
 		for (auto &cell_it : module->cells) {
 			RTLIL::Cell *c = cell_it.second;
 			if (ct.cell_known(c->type) && design->selected(mod, c))
-				for (auto &p : c->connections_) {
+				for (auto &p : c->connections()) {
 					if (ct.cell_output(c->type, p.first))
 						sig2driver.insert(assign_map(p.second), c);
 					else

passes/fsm/fsm_extract.cc

@@ -58,9 +58,9 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
 			log("  unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
 			return false;
 		}
-		RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]);
+		RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-		RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]);
+		RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
-		RTLIL::SigSpec sig_s = assign_map(cell->connections_["\\S"]);
+		RTLIL::SigSpec sig_s = assign_map(cell->get("\\S"));
 		if (reset_state && RTLIL::SigSpec(*reset_state).is_fully_undef())
 			do {
 				if (sig_a.is_fully_def())
@@ -183,12 +183,12 @@ static void extract_fsm(RTLIL::Wire *wire)
 		if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q")
 			continue;
 		log("  found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
-		RTLIL::SigSpec sig_q = assign_map(cell->connections_["\\Q"]);
+		RTLIL::SigSpec sig_q = assign_map(cell->get("\\Q"));
-		RTLIL::SigSpec sig_d = assign_map(cell->connections_["\\D"]);
+		RTLIL::SigSpec sig_d = assign_map(cell->get("\\D"));
-		clk = cell->connections_["\\CLK"];
+		clk = cell->get("\\CLK");
 		clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 		if (cell->type == "$adff") {
-			arst = cell->connections_["\\ARST"];
+			arst = cell->get("\\ARST");
 			arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool();
 			reset_state = cell->parameters["\\ARST_VALUE"];
 		}
@@ -224,9 +224,9 @@ static void extract_fsm(RTLIL::Wire *wire)
 	sig2trigger.find(dff_out, cellport_list);
 	for (auto &cellport : cellport_list) {
 		RTLIL::Cell *cell = module->cells.at(cellport.first);
-		RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]);
+		RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-		RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]);
+		RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
-		RTLIL::SigSpec sig_y = assign_map(cell->connections_["\\Y"]);
+		RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y"));
 		if (cellport.second == "\\A" && !sig_b.is_fully_const())
 			continue;
 		if (cellport.second == "\\B" && !sig_a.is_fully_const())
@@ -271,12 +271,12 @@ static void extract_fsm(RTLIL::Wire *wire)
 	// create fsm cell
 
 	RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++), "$fsm");
-	fsm_cell->connections_["\\CLK"] = clk;
+	fsm_cell->set("\\CLK", clk);
-	fsm_cell->connections_["\\ARST"] = arst;
+	fsm_cell->set("\\ARST", arst);
 	fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1);
 	fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1);
-	fsm_cell->connections_["\\CTRL_IN"] = ctrl_in;
+	fsm_cell->set("\\CTRL_IN", ctrl_in);
-	fsm_cell->connections_["\\CTRL_OUT"] = ctrl_out;
+	fsm_cell->set("\\CTRL_OUT", ctrl_out);
 	fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name);
 	fsm_cell->attributes = wire->attributes;
 	fsm_data.copy_to_cell(fsm_cell);
@@ -294,7 +294,7 @@ static void extract_fsm(RTLIL::Wire *wire)
 	sig2driver.find(ctrl_out, cellport_list);
 	for (auto &cellport : cellport_list) {
 		RTLIL::Cell *cell = module->cells.at(cellport.first);
-		RTLIL::SigSpec port_sig = assign_map(cell->connections_[cellport.second]);
+		RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second));
 		RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
 		RTLIL::Wire *unconn_wire = new RTLIL::Wire;
 		unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++);
@@ -344,14 +344,14 @@ struct FsmExtractPass : public Pass {
 			sig2driver.clear();
 			sig2trigger.clear();
 			for (auto &cell_it : module->cells)
-				for (auto &conn_it : cell_it.second->connections_) {
+				for (auto &conn_it : cell_it.second->connections()) {
 					if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
 						RTLIL::SigSpec sig = conn_it.second;
 						assign_map.apply(sig);
 						sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
 					}
-					if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections_.count("\\Y") > 0 &&
+					if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections().count("\\Y") > 0 &&
-							cell_it.second->connections_["\\Y"].size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
+							cell_it.second->get("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
 						RTLIL::SigSpec sig = conn_it.second;
 						assign_map.apply(sig);
 						sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));

passes/fsm/fsm_map.cc

@@ -58,9 +58,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 			and_sig.append(RTLIL::SigSpec(eq_wire));
 
 			RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
-			eq_cell->connections_["\\A"] = eq_sig_a;
+			eq_cell->set("\\A", eq_sig_a);
-			eq_cell->connections_["\\B"] = eq_sig_b;
+			eq_cell->set("\\B", eq_sig_b);
-			eq_cell->connections_["\\Y"] = RTLIL::SigSpec(eq_wire);
+			eq_cell->set("\\Y", RTLIL::SigSpec(eq_wire));
 			eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size());
@@ -80,8 +80,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 				and_sig.append(RTLIL::SigSpec(or_wire));
 
 				RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
-				or_cell->connections_["\\A"] = or_sig;
+				or_cell->set("\\A", or_sig);
-				or_cell->connections_["\\Y"] = RTLIL::SigSpec(or_wire);
+				or_cell->set("\\Y", RTLIL::SigSpec(or_wire));
 				or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 				or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size());
 				or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
@@ -96,9 +96,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 				cases_vector.append(RTLIL::SigSpec(and_wire));
 
 				RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and");
-				and_cell->connections_["\\A"] = and_sig.extract(0, 1);
+				and_cell->set("\\A", and_sig.extract(0, 1));
-				and_cell->connections_["\\B"] = and_sig.extract(1, 1);
+				and_cell->set("\\B", and_sig.extract(1, 1));
-				and_cell->connections_["\\Y"] = RTLIL::SigSpec(and_wire);
+				and_cell->set("\\Y", RTLIL::SigSpec(and_wire));
 				and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 				and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
 				and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1);
@@ -119,15 +119,15 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 
 	if (cases_vector.size() > 1) {
 		RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
-		or_cell->connections_["\\A"] = cases_vector;
+		or_cell->set("\\A", cases_vector);
-		or_cell->connections_["\\Y"] = output;
+		or_cell->set("\\Y", output);
 		or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 		or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size());
 		or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 	} else if (cases_vector.size() == 1) {
-		module->connections_.push_back(RTLIL::SigSig(output, cases_vector));
+		module->connect(RTLIL::SigSig(output, cases_vector));
 	} else {
-		module->connections_.push_back(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1)));
+		module->connect(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1)));
 	}
 }
 
@@ -138,8 +138,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 	FsmData fsm_data;
 	fsm_data.copy_from_cell(fsm_cell);
 
-	RTLIL::SigSpec ctrl_in = fsm_cell->connections_["\\CTRL_IN"];
+	RTLIL::SigSpec ctrl_in = fsm_cell->get("\\CTRL_IN");
-	RTLIL::SigSpec ctrl_out = fsm_cell->connections_["\\CTRL_OUT"];
+	RTLIL::SigSpec ctrl_out = fsm_cell->get("\\CTRL_OUT");
 
 	// create state register
 
@@ -153,7 +153,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 	RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
 
 	RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
-	if (fsm_cell->connections_["\\ARST"].is_fully_const()) {
+	if (fsm_cell->get("\\ARST").is_fully_const()) {
 		state_dff->type = "$dff";
 	} else {
 		state_dff->type = "$adff";
@@ -162,13 +162,13 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 		for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits)
 			if (bit != RTLIL::State::S1)
 				bit = RTLIL::State::S0;
-		state_dff->connections_["\\ARST"] = fsm_cell->connections_["\\ARST"];
+		state_dff->set("\\ARST", fsm_cell->get("\\ARST"));
 	}
 	state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits);
 	state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"];
-	state_dff->connections_["\\CLK"] = fsm_cell->connections_["\\CLK"];
+	state_dff->set("\\CLK", fsm_cell->get("\\CLK"));
-	state_dff->connections_["\\D"] = RTLIL::SigSpec(next_state_wire);
+	state_dff->set("\\D", RTLIL::SigSpec(next_state_wire));
-	state_dff->connections_["\\Q"] = RTLIL::SigSpec(state_wire);
+	state_dff->set("\\Q", RTLIL::SigSpec(state_wire));
 
 	// decode state register
 
@@ -189,16 +189,16 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 
 		if (sig_b == RTLIL::SigSpec(RTLIL::State::S1))
 		{
-			module->connections_.push_back(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, i), sig_a));
+			module->connect(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, i), sig_a));
 		}
 		else
 		{
 			encoding_is_onehot = false;
 
 			RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
-			eq_cell->connections_["\\A"] = sig_a;
+			eq_cell->set("\\A", sig_a);
-			eq_cell->connections_["\\B"] = sig_b;
+			eq_cell->set("\\B", sig_b);
-			eq_cell->connections_["\\Y"] = RTLIL::SigSpec(state_onehot, i);
+			eq_cell->set("\\Y", RTLIL::SigSpec(state_onehot, i));
 			eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
@@ -245,7 +245,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 				next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i));
 		}
 		log_assert(!next_state_sig.has_marked_bits());
-		module->connections_.push_back(RTLIL::SigSig(next_state_wire, next_state_sig));
+		module->connect(RTLIL::SigSig(next_state_wire, next_state_sig));
 	}
 	else
 	{
@@ -265,10 +265,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 		}
 
 		RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux");
-		mux_cell->connections_["\\A"] = sig_a;
+		mux_cell->set("\\A", sig_a);
-		mux_cell->connections_["\\B"] = sig_b;
+		mux_cell->set("\\B", sig_b);
-		mux_cell->connections_["\\S"] = sig_s;
+		mux_cell->set("\\S", sig_s);
-		mux_cell->connections_["\\Y"] = RTLIL::SigSpec(next_state_wire);
+		mux_cell->set("\\Y", RTLIL::SigSpec(next_state_wire));
 		mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
 		mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
 	}

passes/fsm/fsm_opt.cc

@@ -52,7 +52,7 @@ struct FsmOpt
 
 	void opt_const_and_unused_inputs()
 	{
-		RTLIL::SigSpec ctrl_in = cell->connections_["\\CTRL_IN"];
+		RTLIL::SigSpec ctrl_in = cell->get("\\CTRL_IN");
 		std::vector<bool> ctrl_in_used(ctrl_in.size());
 
 		std::vector<FsmData::transition_t> new_transition_table;
@@ -73,13 +73,15 @@ struct FsmOpt
 
 		for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) {
 			if (!ctrl_in_used[i]) {
-				log("  Removing unused input signal %s.\n", log_signal(cell->connections_["\\CTRL_IN"].extract(i, 1)));
+				log("  Removing unused input signal %s.\n", log_signal(cell->get("\\CTRL_IN").extract(i, 1)));
 				for (auto &tr : new_transition_table) {
 					RTLIL::SigSpec tmp(tr.ctrl_in);
 					tmp.remove(i, 1);
 					tr.ctrl_in = tmp.as_const();
 				}
-				cell->connections_["\\CTRL_IN"].remove(i, 1);
+				RTLIL::SigSpec new_ctrl_in = cell->get("\\CTRL_IN");
+				new_ctrl_in.remove(i, 1);
+				cell->set("\\CTRL_IN", new_ctrl_in);
 				fsm_data.num_inputs--;
 			}
 		}
@@ -91,10 +93,12 @@ struct FsmOpt
 	void opt_unused_outputs()
 	{
 		for (int i = 0; i < fsm_data.num_outputs; i++) {
-			RTLIL::SigSpec sig = cell->connections_["\\CTRL_OUT"].extract(i, 1);
+			RTLIL::SigSpec sig = cell->get("\\CTRL_OUT").extract(i, 1);
 			if (signal_is_unused(sig)) {
 				log("  Removing unused output signal %s.\n", log_signal(sig));
-				cell->connections_["\\CTRL_OUT"].remove(i, 1);
+				RTLIL::SigSpec new_ctrl_out = cell->get("\\CTRL_OUT");
+				new_ctrl_out.remove(i, 1);
+				cell->set("\\CTRL_OUT", new_ctrl_out);
 				for (auto &tr : fsm_data.transition_table) {
 					RTLIL::SigSpec tmp(tr.ctrl_out);
 					tmp.remove(i, 1);

passes/fsm/fsmdata.h

@@ -141,13 +141,13 @@ struct FsmData
 
 		log("\n");
 		log("  Input signals:\n");
-		RTLIL::SigSpec sig_in = cell->connections_["\\CTRL_IN"];
+		RTLIL::SigSpec sig_in = cell->get("\\CTRL_IN");
 		for (int i = 0; i < SIZE(sig_in); i++)
 			log("  %3d: %s\n", i, log_signal(sig_in[i]));
 
 		log("\n");
 		log("  Output signals:\n");
-		RTLIL::SigSpec sig_out = cell->connections_["\\CTRL_OUT"];
+		RTLIL::SigSpec sig_out = cell->get("\\CTRL_OUT");
 		for (int i = 0; i < SIZE(sig_out); i++)
 			log("  %3d: %s\n", i, log_signal(sig_out[i]));
 

passes/hierarchy/hierarchy.cc

@@ -58,7 +58,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 		for (auto i1 : design->modules)
 		for (auto i2 : i1.second->cells)
 			if (i2.second->type == celltype) {
-				for (auto &conn : i2.second->connections_) {
+				for (auto &conn : i2.second->connections()) {
 					if (conn.first[0] != '$')
 						portnames.insert(conn.first);
 					portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.size());
@@ -486,7 +486,7 @@ struct HierarchyPass : public Pass {
 				RTLIL::Cell *cell = cell_it.second;
 				if (design->modules.count(cell->type) == 0)
 					continue;
-				for (auto &conn : cell->connections_)
+				for (auto &conn : cell->connections())
 					if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
 						pos_mods.insert(design->modules.at(cell->type));
 						pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod_it.second, cell));
@@ -507,7 +507,7 @@ struct HierarchyPass : public Pass {
 				log("Mapping positional arguments of cell %s.%s (%s).\n",
 						RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
 				std::map<RTLIL::IdString, RTLIL::SigSpec> new_connections;
-				for (auto &conn : cell->connections_)
+				for (auto &conn : cell->connections())
 					if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
 						int id = atoi(conn.first.c_str()+1);
 						std::pair<RTLIL::Module*,int> key(design->modules.at(cell->type), id);

passes/hierarchy/submod.cc

@@ -65,7 +65,7 @@ struct SubmodWorker
 		flag_found_something = true;
 	}
 
-	void flag_signal(RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
+	void flag_signal(const RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
 	{
 		for (auto &c : sig.chunks())
 			if (c.wire != NULL)
@@ -79,11 +79,11 @@ struct SubmodWorker
 		wire_flags.clear();
 		for (RTLIL::Cell *cell : submod.cells) {
 			if (ct.cell_known(cell->type)) {
-				for (auto &conn : cell->connections_)
+				for (auto &conn : cell->connections())
 					flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false);
 			} else {
 				log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
-				for (auto &conn : cell->connections_)
+				for (auto &conn : cell->connections())
 					flag_signal(conn.second, true, true, true, false, false);
 			}
 		}
@@ -92,11 +92,11 @@ struct SubmodWorker
 			if (submod.cells.count(cell) > 0)
 				continue;
 			if (ct.cell_known(cell->type)) {
-				for (auto &conn : cell->connections_)
+				for (auto &conn : cell->connections())
 					flag_signal(conn.second, false, false, false, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first));
 			} else {
 				flag_found_something = false;
-				for (auto &conn : cell->connections_)
+				for (auto &conn : cell->connections())
 					flag_signal(conn.second, false, false, false, true, true);
 				if (flag_found_something)
 					log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
@@ -180,7 +180,7 @@ struct SubmodWorker
 			RTLIL::Wire *old_wire = it.first;
 			RTLIL::Wire *new_wire = it.second.new_wire;
 			if (new_wire->port_id > 0)
-				new_cell->connections_[new_wire->name] = RTLIL::SigSpec(old_wire);
+				new_cell->set(new_wire->name, RTLIL::SigSpec(old_wire));
 		}
 	}
 

passes/memory/memory_collect.cc

@@ -76,12 +76,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 			wr_ports++;
 			del_cells.push_back(cell);
 
-			RTLIL::SigSpec clk = cell->connections_["\\CLK"];
+			RTLIL::SigSpec clk = cell->get("\\CLK");
 			RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
 			RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
-			RTLIL::SigSpec addr = cell->connections_["\\ADDR"];
+			RTLIL::SigSpec addr = cell->get("\\ADDR");
-			RTLIL::SigSpec data = cell->connections_["\\DATA"];
+			RTLIL::SigSpec data = cell->get("\\DATA");
-			RTLIL::SigSpec en = cell->connections_["\\EN"];
+			RTLIL::SigSpec en = cell->get("\\EN");
 
 			clk.extend(1, false);
 			clk_enable.extend(1, false);
@@ -103,12 +103,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 			rd_ports++;
 			del_cells.push_back(cell);
 
-			RTLIL::SigSpec clk = cell->connections_["\\CLK"];
+			RTLIL::SigSpec clk = cell->get("\\CLK");
 			RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
 			RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
 			RTLIL::SigSpec transparent = RTLIL::SigSpec(cell->parameters["\\TRANSPARENT"]);
-			RTLIL::SigSpec addr = cell->connections_["\\ADDR"];
+			RTLIL::SigSpec addr = cell->get("\\ADDR");
-			RTLIL::SigSpec data = cell->connections_["\\DATA"];
+			RTLIL::SigSpec data = cell->get("\\DATA");
 
 			clk.extend(1, false);
 			clk_enable.extend(1, false);
@@ -147,10 +147,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 	mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0);
 	mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0);
 
-	mem->connections_["\\WR_CLK"] = sig_wr_clk;
+	mem->set("\\WR_CLK", sig_wr_clk);
-	mem->connections_["\\WR_ADDR"] = sig_wr_addr;
+	mem->set("\\WR_ADDR", sig_wr_addr);
-	mem->connections_["\\WR_DATA"] = sig_wr_data;
+	mem->set("\\WR_DATA", sig_wr_data);
-	mem->connections_["\\WR_EN"] = sig_wr_en;
+	mem->set("\\WR_EN", sig_wr_en);
 
 	assert(sig_rd_clk.size() == rd_ports);
 	assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
@@ -163,9 +163,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 	mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0);
 	mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0);
 
-	mem->connections_["\\RD_CLK"] = sig_rd_clk;
+	mem->set("\\RD_CLK", sig_rd_clk);
-	mem->connections_["\\RD_ADDR"] = sig_rd_addr;
+	mem->set("\\RD_ADDR", sig_rd_addr);
-	mem->connections_["\\RD_DATA"] = sig_rd_data;
+	mem->set("\\RD_DATA", sig_rd_data);
 
 	for (auto c : del_cells)
 		module->remove(c);

passes/memory/memory_dff.cc

@@ -25,7 +25,7 @@
 
 static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
 {
-	for (auto &conn : module->connections_)
+	for (auto &conn : module->connections())
 		sig.replace(conn.first, conn.second);
 }
 
@@ -46,21 +46,21 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 				continue;
 
 			if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
-				if (cell->connections_["\\CLK"] != clk)
+				if (cell->get("\\CLK") != clk)
 					continue;
 				if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity)
 					continue;
 			}
 
-			RTLIL::SigSpec q_norm = cell->connections_[after ? "\\D" : "\\Q"];
+			RTLIL::SigSpec q_norm = cell->get(after ? "\\D" : "\\Q");
 			normalize_sig(module, q_norm);
 
-			RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections_[after ? "\\Q" : "\\D"]);
+			RTLIL::SigSpec d = q_norm.extract(bit, &cell->get(after ? "\\Q" : "\\D"));
 			if (d.size() != 1)
 				continue;
 
 			bit = d;
-			clk = cell->connections_["\\CLK"];
+			clk = cell->get("\\CLK");
 			clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 			goto replaced_this_bit;
 		}
@@ -79,29 +79,29 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
 	bool clk_polarity = 0;
 
-	RTLIL::SigSpec sig_addr = cell->connections_["\\ADDR"];
+	RTLIL::SigSpec sig_addr = cell->get("\\ADDR");
 	if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) {
 		log("no (compatible) $dff for address input found.\n");
 		return;
 	}
 
-	RTLIL::SigSpec sig_data = cell->connections_["\\DATA"];
+	RTLIL::SigSpec sig_data = cell->get("\\DATA");
 	if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) {
 		log("no (compatible) $dff for data input found.\n");
 		return;
 	}
 
-	RTLIL::SigSpec sig_en = cell->connections_["\\EN"];
+	RTLIL::SigSpec sig_en = cell->get("\\EN");
 	if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) {
 		log("no (compatible) $dff for enable input found.\n");
 		return;
 	}
 
 	if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
-		cell->connections_["\\CLK"] = clk;
+		cell->set("\\CLK", clk);
-		cell->connections_["\\ADDR"] = sig_addr;
+		cell->set("\\ADDR", sig_addr);
-		cell->connections_["\\DATA"] = sig_data;
+		cell->set("\\DATA", sig_data);
-		cell->connections_["\\EN"] = sig_en;
+		cell->set("\\EN", sig_en);
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		log("merged $dff to cell.\n");
@@ -127,8 +127,11 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 
 	for (auto &cell_it : module->cells) {
 		RTLIL::Cell *cell = cell_it.second;
-		if (cell->type == "$dff")
+		if (cell->type == "$dff") {
-			cell->connections_["\\Q"].replace(sig, newsig);
+			RTLIL::SigSpec new_q = cell->get("\\Q");
+			new_q.replace(sig, newsig);
+			cell->set("\\Q", new_q);
+		}
 	}
 }
 
@@ -139,13 +142,13 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	bool clk_polarity = 0;
 
 	RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
-	RTLIL::SigSpec sig_data = cell->connections_["\\DATA"];
+	RTLIL::SigSpec sig_data = cell->get("\\DATA");
 	if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) &&
 			clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
 	{
 		disconnect_dff(module, sig_data);
-		cell->connections_["\\CLK"] = clk_data;
+		cell->set("\\CLK", clk_data);
-		cell->connections_["\\DATA"] = sig_data;
+		cell->set("\\DATA", sig_data);
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
@@ -154,12 +157,12 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 
 	RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
-	RTLIL::SigSpec sig_addr = cell->connections_["\\ADDR"];
+	RTLIL::SigSpec sig_addr = cell->get("\\ADDR");
 	if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) &&
 			clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
 	{
-		cell->connections_["\\CLK"] = clk_addr;
+		cell->set("\\CLK", clk_addr);
-		cell->connections_["\\ADDR"] = sig_addr;
+		cell->set("\\ADDR", sig_addr);
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);

passes/memory/memory_map.cc

@@ -62,20 +62,20 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 
 	// all write ports must share the same clock
-	RTLIL::SigSpec clocks = cell->connections_["\\WR_CLK"];
+	RTLIL::SigSpec clocks = cell->get("\\WR_CLK");
 	RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"];
 	RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
 	RTLIL::SigSpec refclock;
 	RTLIL::State refclock_pol = RTLIL::State::Sx;
 	for (int i = 0; i < clocks.size(); i++) {
-		RTLIL::SigSpec wr_en = cell->connections_["\\WR_EN"].extract(i * mem_width, mem_width);
+		RTLIL::SigSpec wr_en = cell->get("\\WR_EN").extract(i * mem_width, mem_width);
 		if (wr_en.is_fully_const() && !wr_en.as_bool()) {
 			static_ports.insert(i);
 			continue;
 		}
 		if (clocks_en.bits[i] != RTLIL::State::S1) {
-			RTLIL::SigSpec wr_addr = cell->connections_["\\WR_ADDR"].extract(i*mem_abits, mem_abits);
+			RTLIL::SigSpec wr_addr = cell->get("\\WR_ADDR").extract(i*mem_abits, mem_abits);
-			RTLIL::SigSpec wr_data = cell->connections_["\\WR_DATA"].extract(i*mem_width, mem_width);
+			RTLIL::SigSpec wr_data = cell->get("\\WR_DATA").extract(i*mem_width, mem_width);
 			if (wr_addr.is_fully_const()) {
 				// FIXME: Actually we should check for wr_en.is_fully_const() also and
 				// create a $adff cell with this ports wr_en input as reset pin when wr_en
@@ -120,10 +120,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 			c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
 			if (clocks_pol.bits.size() > 0) {
 				c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
-				c->connections_["\\CLK"] = clocks.extract(0, 1);
+				c->set("\\CLK", clocks.extract(0, 1));
 			} else {
 				c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1);
-				c->connections_["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0);
+				c->set("\\CLK", RTLIL::SigSpec(RTLIL::State::S0));
 			}
 
 			RTLIL::Wire *w_in = new RTLIL::Wire;
@@ -131,7 +131,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 			w_in->width = mem_width;
 			module->wires[w_in->name] = w_in;
 			data_reg_in.push_back(RTLIL::SigSpec(w_in));
-			c->connections_["\\D"] = data_reg_in.back();
+			c->set("\\D", data_reg_in.back());
 
 			RTLIL::Wire *w_out = new RTLIL::Wire;
 			w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
@@ -141,7 +141,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 			w_out->start_offset = mem_offset;
 			module->wires[w_out->name] = w_out;
 			data_reg_out.push_back(RTLIL::SigSpec(w_out));
-			c->connections_["\\Q"] = data_reg_out.back();
+			c->set("\\Q", data_reg_out.back());
 		}
 	}
 
@@ -151,10 +151,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++)
 	{
-		RTLIL::SigSpec rd_addr = cell->connections_["\\RD_ADDR"].extract(i*mem_abits, mem_abits);
+		RTLIL::SigSpec rd_addr = cell->get("\\RD_ADDR").extract(i*mem_abits, mem_abits);
 
 		std::vector<RTLIL::SigSpec> rd_signals;
-		rd_signals.push_back(cell->connections_["\\RD_DATA"].extract(i*mem_width, mem_width));
+		rd_signals.push_back(cell->get("\\RD_DATA").extract(i*mem_width, mem_width));
 
 		if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1)
 		{
@@ -163,8 +163,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 				RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
 				c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits);
 				c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
-				c->connections_["\\CLK"] = cell->connections_["\\RD_CLK"].extract(i, 1);
+				c->set("\\CLK", cell->get("\\RD_CLK").extract(i, 1));
-				c->connections_["\\D"] = rd_addr;
+				c->set("\\D", rd_addr);
 				count_dff++;
 
 				RTLIL::Wire *w = new RTLIL::Wire;
@@ -172,7 +172,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 				w->width = mem_abits;
 				module->wires[w->name] = w;
 
-				c->connections_["\\Q"] = RTLIL::SigSpec(w);
+				c->set("\\Q", RTLIL::SigSpec(w));
 				rd_addr = RTLIL::SigSpec(w);
 			}
 			else
@@ -180,8 +180,8 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 				RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
 				c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
 				c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
-				c->connections_["\\CLK"] = cell->connections_["\\RD_CLK"].extract(i, 1);
+				c->set("\\CLK", cell->get("\\RD_CLK").extract(i, 1));
-				c->connections_["\\Q"] = rd_signals.back();
+				c->set("\\Q", rd_signals.back());
 				count_dff++;
 
 				RTLIL::Wire *w = new RTLIL::Wire;
@@ -191,7 +191,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 
 				rd_signals.clear();
 				rd_signals.push_back(RTLIL::SigSpec(w));
-				c->connections_["\\D"] = rd_signals.back();
+				c->set("\\D", rd_signals.back());
 			}
 		}
 
@@ -203,31 +203,31 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 			{
 				RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux");
 				c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
-				c->connections_["\\Y"] = rd_signals[k];
+				c->set("\\Y", rd_signals[k]);
-				c->connections_["\\S"] = rd_addr.extract(mem_abits-j-1, 1);
+				c->set("\\S", rd_addr.extract(mem_abits-j-1, 1));
 				count_mux++;
 
 				RTLIL::Wire *w = new RTLIL::Wire;
 				w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$a");
 				w->width = mem_width;
 				module->wires[w->name] = w;
-				c->connections_["\\A"] = RTLIL::SigSpec(w);
+				c->set("\\A", RTLIL::SigSpec(w));
 
 				w = new RTLIL::Wire;
 				w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$b");
 				w->width = mem_width;
 				module->wires[w->name] = w;
-				c->connections_["\\B"] = RTLIL::SigSpec(w);
+				c->set("\\B", RTLIL::SigSpec(w));
 
-				next_rd_signals.push_back(c->connections_["\\A"]);
+				next_rd_signals.push_back(c->get("\\A"));
-				next_rd_signals.push_back(c->connections_["\\B"]);
+				next_rd_signals.push_back(c->get("\\B"));
 			}
 
 			next_rd_signals.swap(rd_signals);
 		}
 
 		for (int j = 0; j < mem_size; j++)
-			module->connections_.push_back(RTLIL::SigSig(rd_signals[j], data_reg_out[j]));
+			module->connect(RTLIL::SigSig(rd_signals[j], data_reg_out[j]));
 	}
 
 	log("  read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux);
@@ -241,9 +241,9 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 
 		for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++)
 		{
-			RTLIL::SigSpec wr_addr = cell->connections_["\\WR_ADDR"].extract(j*mem_abits, mem_abits);
+			RTLIL::SigSpec wr_addr = cell->get("\\WR_ADDR").extract(j*mem_abits, mem_abits);
-			RTLIL::SigSpec wr_data = cell->connections_["\\WR_DATA"].extract(j*mem_width, mem_width);
+			RTLIL::SigSpec wr_data = cell->get("\\WR_DATA").extract(j*mem_width, mem_width);
-			RTLIL::SigSpec wr_en = cell->connections_["\\WR_EN"].extract(j*mem_width, mem_width);
+			RTLIL::SigSpec wr_en = cell->get("\\WR_EN").extract(j*mem_width, mem_width);
 
 			RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq");
 			c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
@@ -251,14 +251,14 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 			c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"];
 			c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"];
 			c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-			c->connections_["\\A"] = RTLIL::SigSpec(i, mem_abits);
+			c->set("\\A", RTLIL::SigSpec(i, mem_abits));
-			c->connections_["\\B"] = wr_addr;
+			c->set("\\B", wr_addr);
 			count_wrmux++;
 
 			RTLIL::Wire *w_seladdr = new RTLIL::Wire;
 			w_seladdr->name = genid(cell->name, "$wreq", i, "", j, "$y");
 			module->wires[w_seladdr->name] = w_seladdr;
-			c->connections_["\\Y"] = w_seladdr;
+			c->set("\\Y", w_seladdr);
 
 			int wr_offset = 0;
 			while (wr_offset < wr_en.size())
@@ -283,33 +283,33 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 					c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
 					c->parameters["\\B_WIDTH"] = RTLIL::Const(1);
 					c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-					c->connections_["\\A"] = w;
+					c->set("\\A", w);
-					c->connections_["\\B"] = wr_bit;
+					c->set("\\B", wr_bit);
 
 					w = new RTLIL::Wire;
 					w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y");
 					module->wires[w->name] = w;
-					c->connections_["\\Y"] = RTLIL::SigSpec(w);
+					c->set("\\Y", RTLIL::SigSpec(w));
 				}
 
 				c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux");
 				c->parameters["\\WIDTH"] = wr_width;
-				c->connections_["\\A"] = sig.extract(wr_offset, wr_width);
+				c->set("\\A", sig.extract(wr_offset, wr_width));
-				c->connections_["\\B"] = wr_data.extract(wr_offset, wr_width);
+				c->set("\\B", wr_data.extract(wr_offset, wr_width));
-				c->connections_["\\S"] = RTLIL::SigSpec(w);
+				c->set("\\S", RTLIL::SigSpec(w));
 
 				w = new RTLIL::Wire;
 				w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y");
 				w->width = wr_width;
 				module->wires[w->name] = w;
-				c->connections_["\\Y"] = w;
+				c->set("\\Y", w);
 
 				sig.replace(wr_offset, w);
 				wr_offset += wr_width;
 			}
 		}
 
-		module->connections_.push_back(RTLIL::SigSig(data_reg_in[i], sig));
+		module->connect(RTLIL::SigSig(data_reg_in[i], sig));
 	}
 
 	log("  write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux);

passes/memory/memory_share.cc

@@ -64,16 +64,19 @@ struct MemoryShareWorker
 		RTLIL::Cell *cell = sig_to_mux.at(sig).first;
 		int bit_idx = sig_to_mux.at(sig).second;
 
-		std::vector<RTLIL::SigBit> sig_a = sigmap(cell->connections_.at("\\A"));
+		std::vector<RTLIL::SigBit> sig_a = sigmap(cell->get("\\A"));
-		std::vector<RTLIL::SigBit> sig_b = sigmap(cell->connections_.at("\\B"));
+		std::vector<RTLIL::SigBit> sig_b = sigmap(cell->get("\\B"));
-		std::vector<RTLIL::SigBit> sig_s = sigmap(cell->connections_.at("\\S"));
+		std::vector<RTLIL::SigBit> sig_s = sigmap(cell->get("\\S"));
-		std::vector<RTLIL::SigBit> sig_y = sigmap(cell->connections_.at("\\Y"));
+		std::vector<RTLIL::SigBit> sig_y = sigmap(cell->get("\\Y"));
 		log_assert(sig_y.at(bit_idx) == sig);
 
 		for (int i = 0; i < int(sig_s.size()); i++)
 			if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) {
-				if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions))
+				if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) {
-					cell->connections_.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
+					RTLIL::SigSpec new_b = cell->get("\\B");
+					new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
+					cell->set("\\B", new_b);
+				}
 				return false;
 			}
 				
@@ -86,16 +89,22 @@ struct MemoryShareWorker
 			std::map<RTLIL::SigBit, bool> new_state = state;
 			new_state[sig_s[i]] = true;
 
-			if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions))
+			if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) {
-				cell->connections_.at("\\B").replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
+				RTLIL::SigSpec new_b = cell->get("\\B");
+				new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
+				cell->set("\\B", new_b);
+			}
 		}
 
 		std::map<RTLIL::SigBit, bool> new_state = state;
 		for (int i = 0; i < int(sig_s.size()); i++)
 			new_state[sig_s[i]] = false;
 
-		if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions))
+		if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) {
-			cell->connections_.at("\\A").replace(bit_idx, RTLIL::State::Sx);
+			RTLIL::SigSpec new_a = cell->get("\\A");
+			new_a.replace(bit_idx, RTLIL::State::Sx);
+			cell->set("\\A", new_a);
+		}
 
 		return false;
 	}
@@ -141,10 +150,10 @@ struct MemoryShareWorker
 
 			if (cell->type == "$mux" || cell->type == "$pmux")
 			{
-				std::vector<RTLIL::SigBit> sig_a = sigmap(cell->connections_.at("\\A"));
+				std::vector<RTLIL::SigBit> sig_a = sigmap(cell->get("\\A"));
-				std::vector<RTLIL::SigBit> sig_b = sigmap(cell->connections_.at("\\B"));
+				std::vector<RTLIL::SigBit> sig_b = sigmap(cell->get("\\B"));
-				std::vector<RTLIL::SigBit> sig_s = sigmap(cell->connections_.at("\\S"));
+				std::vector<RTLIL::SigBit> sig_s = sigmap(cell->get("\\S"));
-				std::vector<RTLIL::SigBit> sig_y = sigmap(cell->connections_.at("\\Y"));
+				std::vector<RTLIL::SigBit> sig_y = sigmap(cell->get("\\Y"));
 
 				non_feedback_nets.insert(sig_s.begin(), sig_s.end());
 
@@ -161,7 +170,7 @@ struct MemoryShareWorker
 					cell->parameters.at("\\MEMID").decode_string() == memid)
 				ignore_data_port = true;
 
-			for (auto conn : cell_it.second->connections_)
+			for (auto conn : cell_it.second->connections())
 			{
 				if (ignore_data_port && conn.first == "\\DATA")
 					continue;
@@ -191,8 +200,8 @@ struct MemoryShareWorker
 			if (cell->parameters.at("\\CLK_ENABLE").as_bool())
 				continue;
 
-			RTLIL::SigSpec sig_addr = sigmap(cell->connections_.at("\\ADDR"));
+			RTLIL::SigSpec sig_addr = sigmap(cell->get("\\ADDR"));
-			std::vector<RTLIL::SigBit> sig_data = sigmap(cell->connections_.at("\\DATA"));
+			std::vector<RTLIL::SigBit> sig_data = sigmap(cell->get("\\DATA"));
 
 			for (int i = 0; i < int(sig_data.size()); i++)
 				if (non_feedback_nets.count(sig_data[i]))
@@ -212,14 +221,14 @@ struct MemoryShareWorker
 
 		for (auto cell : wr_ports)
 		{
-			RTLIL::SigSpec sig_addr = sigmap_xmux(cell->connections_.at("\\ADDR"));
+			RTLIL::SigSpec sig_addr = sigmap_xmux(cell->get("\\ADDR"));
 			if (!async_rd_bits.count(sig_addr))
 				continue;
 
 			log("  Analyzing write port %s.\n", log_id(cell));
 
-			std::vector<RTLIL::SigBit> cell_data = cell->connections_.at("\\DATA");
+			std::vector<RTLIL::SigBit> cell_data = cell->get("\\DATA");
-			std::vector<RTLIL::SigBit> cell_en = cell->connections_.at("\\EN");
+			std::vector<RTLIL::SigBit> cell_en = cell->get("\\EN");
 
 			int created_conditions = 0;
 			for (int i = 0; i < int(cell_data.size()); i++)
@@ -239,7 +248,7 @@ struct MemoryShareWorker
 
 			if (created_conditions) {
 				log("    Added enable logic for %d different cases.\n", created_conditions);
-				cell->connections_.at("\\EN") = cell_en;
+				cell->set("\\EN", cell_en);
 			}
 		}
 	}
@@ -357,15 +366,15 @@ struct MemoryShareWorker
 		for (int i = 0; i < int(wr_ports.size()); i++)
 		{
 			RTLIL::Cell *cell = wr_ports.at(i);
-			RTLIL::SigSpec addr = sigmap_xmux(cell->connections_.at("\\ADDR"));
+			RTLIL::SigSpec addr = sigmap_xmux(cell->get("\\ADDR"));
 
 			if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
-					(cache_clk_enable && (sigmap(cell->connections_.at("\\CLK")) != cache_clk ||
+					(cache_clk_enable && (sigmap(cell->get("\\CLK")) != cache_clk ||
 					cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
 			{
 				cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
 				cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
-				cache_clk = sigmap(cell->connections_.at("\\CLK"));
+				cache_clk = sigmap(cell->get("\\CLK"));
 				last_port_by_addr.clear();
 
 				if (cache_clk_enable)
@@ -377,7 +386,7 @@ struct MemoryShareWorker
 			log("    Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr));
 
 			log("      Active bits: ");
-			std::vector<RTLIL::SigBit> en_bits = sigmap(cell->connections_.at("\\EN"));
+			std::vector<RTLIL::SigBit> en_bits = sigmap(cell->get("\\EN"));
 			active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
 			for (int k = int(en_bits.size())-1; k >= 0; k--) {
 				active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0;
@@ -399,13 +408,13 @@ struct MemoryShareWorker
 
 				// Force this ports addr input to addr directly (skip don't care muxes)
 
-				cell->connections_.at("\\ADDR") = addr;
+				cell->set("\\ADDR", addr);
 
 				// If any of the ports between `last_i' and `i' write to the same address, this
 				// will have priority over whatever `last_i` wrote. So we need to revisit those
 				// ports and mask the EN bits accordingly.
 
-				RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->connections_.at("\\EN"));
+				RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->get("\\EN"));
 
 				for (int j = last_i+1; j < i; j++)
 				{
@@ -420,20 +429,20 @@ struct MemoryShareWorker
 				found_overlapping_bits_i_j:
 						log("      Creating collosion-detect logic for port %d.\n", j);
 						RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID);
-						module->addEq(NEW_ID, addr, wr_ports[j]->connections_.at("\\ADDR"), is_same_addr);
+						module->addEq(NEW_ID, addr, wr_ports[j]->get("\\ADDR"), is_same_addr);
-						merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->connections_.at("\\EN")));
+						merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->get("\\EN")));
 					}
 				}
 
 				// Then we need to merge the (masked) EN and the DATA signals.
 
-				RTLIL::SigSpec merged_data = wr_ports[last_i]->connections_.at("\\DATA");
+				RTLIL::SigSpec merged_data = wr_ports[last_i]->get("\\DATA");
 				if (found_overlapping_bits) {
 					log("      Creating logic for merging DATA and EN ports.\n");
-					merge_en_data(merged_en, merged_data, sigmap(cell->connections_.at("\\EN")), sigmap(cell->connections_.at("\\DATA")));
+					merge_en_data(merged_en, merged_data, sigmap(cell->get("\\EN")), sigmap(cell->get("\\DATA")));
 				} else {
-					RTLIL::SigSpec cell_en = sigmap(cell->connections_.at("\\EN"));
+					RTLIL::SigSpec cell_en = sigmap(cell->get("\\EN"));
-					RTLIL::SigSpec cell_data = sigmap(cell->connections_.at("\\DATA"));
+					RTLIL::SigSpec cell_data = sigmap(cell->get("\\DATA"));
 					for (int k = 0; k < int(en_bits.size()); k++)
 						if (!active_bits_on_port[last_i][k]) {
 							merged_en.replace(k, cell_en.extract(k, 1));
@@ -443,14 +452,14 @@ struct MemoryShareWorker
 
 				// Connect the new EN and DATA signals and remove the old write port.
 
-				cell->connections_.at("\\EN") = merged_en;
+				cell->set("\\EN", merged_en);
-				cell->connections_.at("\\DATA") = merged_data;
+				cell->set("\\DATA", merged_data);
 
 				module->remove(wr_ports[last_i]);
 				wr_ports[last_i] = NULL;
 
 				log("      Active bits: ");
-				std::vector<RTLIL::SigBit> en_bits = sigmap(cell->connections_.at("\\EN"));
+				std::vector<RTLIL::SigBit> en_bits = sigmap(cell->get("\\EN"));
 				active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
 				for (int k = int(en_bits.size())-1; k >= 0; k--)
 					log("%c", active_bits_on_port[i][k] ? '1' : '0');
@@ -489,7 +498,7 @@ struct MemoryShareWorker
 		std::set<int> considered_port_pairs;
 
 		for (int i = 0; i < int(wr_ports.size()); i++) {
-			std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN"));
+			std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->get("\\EN"));
 			for (auto bit : bits)
 				if (bit == RTLIL::State::S1)
 					goto port_is_always_active;
@@ -509,12 +518,12 @@ struct MemoryShareWorker
 			RTLIL::Cell *cell = wr_ports.at(i);
 
 			if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
-					(cache_clk_enable && (sigmap(cell->connections_.at("\\CLK")) != cache_clk ||
+					(cache_clk_enable && (sigmap(cell->get("\\CLK")) != cache_clk ||
 					cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
 			{
 				cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
 				cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
-				cache_clk = sigmap(cell->connections_.at("\\CLK"));
+				cache_clk = sigmap(cell->get("\\CLK"));
 			}
 			else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i))
 				considered_port_pairs.insert(i);
@@ -542,7 +551,7 @@ struct MemoryShareWorker
 		for (int i = 0; i < int(wr_ports.size()); i++)
 			if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1))
 			{
-				RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN"));
+				RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->get("\\EN"));
 				port_to_sat_variable[i] = ez.expression(ez.OpOr, satgen.importSigSpec(sig));
 
 				std::vector<RTLIL::SigBit> bits = sig;
@@ -585,18 +594,18 @@ struct MemoryShareWorker
 			log("  Merging port %d into port %d.\n", i-1, i);
 			port_to_sat_variable.at(i) = ez.OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i));
 
-			RTLIL::SigSpec last_addr = wr_ports[i-1]->connections_.at("\\ADDR");
+			RTLIL::SigSpec last_addr = wr_ports[i-1]->get("\\ADDR");
-			RTLIL::SigSpec last_data = wr_ports[i-1]->connections_.at("\\DATA");
+			RTLIL::SigSpec last_data = wr_ports[i-1]->get("\\DATA");
-			std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->connections_.at("\\EN"));
+			std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->get("\\EN"));
 
-			RTLIL::SigSpec this_addr = wr_ports[i]->connections_.at("\\ADDR");
+			RTLIL::SigSpec this_addr = wr_ports[i]->get("\\ADDR");
-			RTLIL::SigSpec this_data = wr_ports[i]->connections_.at("\\DATA");
+			RTLIL::SigSpec this_data = wr_ports[i]->get("\\DATA");
-			std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->connections_.at("\\EN"));
+			std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->get("\\EN"));
 
 			RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
 
-			wr_ports[i]->connections_.at("\\ADDR") = module->Mux(NEW_ID, last_addr, this_addr, this_en_active);
+			wr_ports[i]->set("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
-			wr_ports[i]->connections_.at("\\DATA") = module->Mux(NEW_ID, last_data, this_data, this_en_active);
+			wr_ports[i]->set("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active));
 
 			std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
 			RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
@@ -614,7 +623,7 @@ struct MemoryShareWorker
 			}
 
 			module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
-			wr_ports[i]->connections_.at("\\EN") = en;
+			wr_ports[i]->set("\\EN", en);
 
 			module->remove(wr_ports[i-1]);
 			wr_ports[i-1] = NULL;
@@ -653,18 +662,18 @@ struct MemoryShareWorker
 
 			if (cell->type == "$mux")
 			{
-				RTLIL::SigSpec sig_a = sigmap_xmux(cell->connections_.at("\\A"));
+				RTLIL::SigSpec sig_a = sigmap_xmux(cell->get("\\A"));
-				RTLIL::SigSpec sig_b = sigmap_xmux(cell->connections_.at("\\B"));
+				RTLIL::SigSpec sig_b = sigmap_xmux(cell->get("\\B"));
 
 				if (sig_a.is_fully_undef())
-					sigmap_xmux.add(cell->connections_.at("\\Y"), sig_b);
+					sigmap_xmux.add(cell->get("\\Y"), sig_b);
 				else if (sig_b.is_fully_undef())
-					sigmap_xmux.add(cell->connections_.at("\\Y"), sig_a);
+					sigmap_xmux.add(cell->get("\\Y"), sig_a);
 			}
 
 			if (cell->type == "$mux" || cell->type == "$pmux")
 			{
-				std::vector<RTLIL::SigBit> sig_y = sigmap(cell->connections_.at("\\Y"));
+				std::vector<RTLIL::SigBit> sig_y = sigmap(cell->get("\\Y"));
 				for (int i = 0; i < int(sig_y.size()); i++)
 					sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i);
 			}

passes/memory/memory_unpack.cc

@@ -54,9 +54,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const();
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const();
 		cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const();
-		cell->connections_["\\CLK"] = memory->connections_.at("\\RD_CLK").extract(i, 1);
+		cell->set("\\CLK", memory->get("\\RD_CLK").extract(i, 1));
-		cell->connections_["\\ADDR"] = memory->connections_.at("\\RD_ADDR").extract(i*abits, abits);
+		cell->set("\\ADDR", memory->get("\\RD_ADDR").extract(i*abits, abits));
-		cell->connections_["\\DATA"] = memory->connections_.at("\\RD_DATA").extract(i*mem->width, mem->width);
+		cell->set("\\DATA", memory->get("\\RD_DATA").extract(i*mem->width, mem->width));
 	}
 
 	for (int i = 0; i < num_wr_ports; i++)
@@ -68,10 +68,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const();
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const();
 		cell->parameters["\\PRIORITY"] = i;
-		cell->connections_["\\CLK"] = memory->connections_.at("\\WR_CLK").extract(i, 1);
+		cell->set("\\CLK", memory->get("\\WR_CLK").extract(i, 1));
-		cell->connections_["\\EN"] = memory->connections_.at("\\WR_EN").extract(i*mem->width, mem->width);
+		cell->set("\\EN", memory->get("\\WR_EN").extract(i*mem->width, mem->width));
-		cell->connections_["\\ADDR"] = memory->connections_.at("\\WR_ADDR").extract(i*abits, abits);
+		cell->set("\\ADDR", memory->get("\\WR_ADDR").extract(i*abits, abits));
-		cell->connections_["\\DATA"] = memory->connections_.at("\\WR_DATA").extract(i*mem->width, mem->width);
+		cell->set("\\DATA", memory->get("\\WR_DATA").extract(i*mem->width, mem->width));
 	}
 
 	module->remove(memory);

passes/opt/opt_clean.cc

@@ -40,7 +40,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
 	SigSet<RTLIL::Cell*> wire2driver;
 	for (auto &it : module->cells) {
 		RTLIL::Cell *cell = it.second;
-		for (auto &it2 : cell->connections_) {
+		for (auto &it2 : cell->connections()) {
 			if (!ct.cell_input(cell->type, it2.first)) {
 				RTLIL::SigSpec sig = it2.second;
 				assign_map.apply(sig);
@@ -70,7 +70,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
 		for (auto cell : queue)
 			unused.erase(cell);
 		for (auto cell : queue) {
-			for (auto &it : cell->connections_) {
+			for (auto &it : cell->connections()) {
 				if (!ct.cell_output(cell->type, it.first)) {
 					std::set<RTLIL::Cell*> cell_list;
 					RTLIL::SigSpec sig = it.second;
@@ -158,10 +158,10 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 		for (auto &it : module->cells) {
 			RTLIL::Cell *cell = it.second;
 			if (ct_reg.cell_known(cell->type))
-				for (auto &it2 : cell->connections_)
+				for (auto &it2 : cell->connections())
 					if (ct_reg.cell_output(cell->type, it2.first))
 						register_signals.add(it2.second);
-			for (auto &it2 : cell->connections_)
+			for (auto &it2 : cell->connections())
 				connected_signals.add(it2.second);
 		}
 	
@@ -171,7 +171,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 	for (auto &it : module->cells) {
 		RTLIL::Cell *cell = it.second;
 		if (ct_all.cell_known(cell->type))
-			for (auto &it2 : cell->connections_)
+			for (auto &it2 : cell->connections())
 				if (ct_all.cell_output(cell->type, it2.first))
 					direct_sigs.insert(assign_map(it2.second));
 	}
@@ -237,7 +237,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 				if (new_conn.first.size() > 0) {
 					used_signals.add(new_conn.first);
 					used_signals.add(new_conn.second);
-					module->connections_.push_back(new_conn);
+					module->connect(new_conn);
 				}
 			}
 		} else {

passes/opt/opt_const.cc

@@ -38,7 +38,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
 	SigPool all_signals;
 
 	for (auto &it : module->cells)
-	for (auto &conn : it.second->connections_) {
+	for (auto &conn : it.second->connections()) {
 		if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
 			driven_signals.add(sigmap(conn.second));
 		if (!ct.cell_known(it.second->type) || ct.cell_input(it.second->type, conn.first))
@@ -66,21 +66,21 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
 			continue;
 
 		log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c));
-		module->connections_.push_back(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width)));
+		module->connect(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width)));
 		OPT_DID_SOMETHING = true;
 	}
 }
 
 static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
 {
-	RTLIL::SigSpec Y = cell->connections_[out_port];
+	RTLIL::SigSpec Y = cell->get(out_port);
 	out_val.extend_u0(Y.size(), false);
 
 	log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
 			cell->type.c_str(), cell->name.c_str(), info.c_str(),
 			module->name.c_str(), log_signal(Y), log_signal(out_val));
 	// ILANG_BACKEND::dump_cell(stderr, "--> ", cell);
-	module->connections_.push_back(RTLIL::SigSig(Y, out_val));
+	module->connect(RTLIL::SigSig(Y, out_val));
 	module->remove(cell);
 	OPT_DID_SOMETHING = true;
 	did_something = true;
@@ -88,14 +88,14 @@ static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string i
 
 static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap)
 {
-	std::string b_name = cell->connections_.count("\\B") ? "\\B" : "\\A";
+	std::string b_name = cell->connections().count("\\B") ? "\\B" : "\\A";
 
 	bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool();
 	bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool();
 
-	RTLIL::SigSpec sig_a = sigmap(cell->connections_.at("\\A"));
+	RTLIL::SigSpec sig_a = sigmap(cell->get("\\A"));
-	RTLIL::SigSpec sig_b = sigmap(cell->connections_.at(b_name));
+	RTLIL::SigSpec sig_b = sigmap(cell->connections().at(b_name));
-	RTLIL::SigSpec sig_y = sigmap(cell->connections_.at("\\Y"));
+	RTLIL::SigSpec sig_y = sigmap(cell->get("\\Y"));
 
 	if (extend_u0) {
 		sig_a.extend_u0(sig_y.size(), a_signed);
@@ -160,21 +160,21 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
 
 		RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
 
-		c->connections_["\\A"] = new_a;
+		c->set("\\A", new_a);
 		c->parameters["\\A_WIDTH"] = new_a.size();
 		c->parameters["\\A_SIGNED"] = false;
 
 		if (b_name == "\\B") {
-			c->connections_["\\B"] = new_b;
+			c->set("\\B", new_b);
 			c->parameters["\\B_WIDTH"] = new_b.size();
 			c->parameters["\\B_SIGNED"] = false;
 		}
 
-		c->connections_["\\Y"] = new_y;
+		c->set("\\Y", new_y);
 		c->parameters["\\Y_WIDTH"] = new_y->width;
 		c->check();
 
-		module->connections_.push_back(new_conn);
+		module->connect(new_conn);
 
 		log("  New cell `%s': A=%s", log_id(c), log_signal(new_a));
 		if (b_name == "\\B")
@@ -203,8 +203,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 	for (auto &cell_it : module->cells)
 		if (design->selected(module, cell_it.second)) {
 			if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") &&
-					cell_it.second->connections_["\\A"].size() == 1 && cell_it.second->connections_["\\Y"].size() == 1)
+					cell_it.second->get("\\A").size() == 1 && cell_it.second->get("\\Y").size() == 1)
-				invert_map[assign_map(cell_it.second->connections_["\\Y"])] = assign_map(cell_it.second->connections_["\\A"]);
+				invert_map[assign_map(cell_it.second->get("\\Y"))] = assign_map(cell_it.second->get("\\A"));
 			cells.push_back(cell_it.second);
 		}
 
@@ -222,7 +222,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$reduce_and")
 			{
-				RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A"));
+				RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
 
 				RTLIL::State new_a = RTLIL::State::S1;
 				for (auto &bit : sig_a.to_sigbit_vector())
@@ -240,7 +240,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover("opt.opt_const.fine.$reduce_and");
 					log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
-					cell->connections_.at("\\A") = sig_a = new_a;
+					cell->set("\\A", sig_a = new_a);
 					cell->parameters.at("\\A_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -249,7 +249,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$logic_not" || cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$reduce_or" || cell->type == "$reduce_bool")
 			{
-				RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A"));
+				RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
 
 				RTLIL::State new_a = RTLIL::State::S0;
 				for (auto &bit : sig_a.to_sigbit_vector())
@@ -267,7 +267,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type);
 					log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
-					cell->connections_.at("\\A") = sig_a = new_a;
+					cell->set("\\A", sig_a = new_a);
 					cell->parameters.at("\\A_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -276,7 +276,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$logic_and" || cell->type == "$logic_or")
 			{
-				RTLIL::SigSpec sig_b = assign_map(cell->connections_.at("\\B"));
+				RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
 
 				RTLIL::State new_b = RTLIL::State::S0;
 				for (auto &bit : sig_b.to_sigbit_vector())
@@ -294,7 +294,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type);
 					log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
-					cell->connections_.at("\\B") = sig_b = new_b;
+					cell->set("\\B", sig_b = new_b);
 					cell->parameters.at("\\B_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -302,13 +302,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			}
 		}
 
-		if (cell->type == "$logic_or" && (assign_map(cell->connections_.at("\\A")) == RTLIL::State::S1 || assign_map(cell->connections_.at("\\B")) == RTLIL::State::S1)) {
+		if (cell->type == "$logic_or" && (assign_map(cell->get("\\A")) == RTLIL::State::S1 || assign_map(cell->get("\\B")) == RTLIL::State::S1)) {
 			cover("opt.opt_const.one_high");
 			replace_cell(module, cell, "one high", "\\Y", RTLIL::State::S1);
 			goto next_cell;
 		}
 
-		if (cell->type == "$logic_and" && (assign_map(cell->connections_.at("\\A")) == RTLIL::State::S0 || assign_map(cell->connections_.at("\\B")) == RTLIL::State::S0)) {
+		if (cell->type == "$logic_and" && (assign_map(cell->get("\\A")) == RTLIL::State::S0 || assign_map(cell->get("\\B")) == RTLIL::State::S0)) {
 			cover("opt.opt_const.one_low");
 			replace_cell(module, cell, "one low", "\\Y", RTLIL::State::S0);
 			goto next_cell;
@@ -320,8 +320,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 				cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" ||
 				cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow")
 		{
-			RTLIL::SigSpec sig_a = assign_map(cell->connections_.at("\\A"));
+			RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-			RTLIL::SigSpec sig_b = cell->connections_.count("\\B") ? assign_map(cell->connections_.at("\\B")) : RTLIL::SigSpec();
+			RTLIL::SigSpec sig_b = cell->connections().count("\\B") ? assign_map(cell->get("\\B")) : RTLIL::SigSpec();
 
 			if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr")
 				sig_a = RTLIL::SigSpec();
@@ -342,31 +342,31 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 						cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt")
 					replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx);
 				else
-					replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->connections_.at("\\Y").size()));
+					replace_cell(module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->get("\\Y").size()));
 				goto next_cell;
 			}
 		}
 
-		if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->connections_["\\Y"].size() == 1 &&
+		if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->get("\\Y").size() == 1 &&
-				invert_map.count(assign_map(cell->connections_["\\A"])) != 0) {
+				invert_map.count(assign_map(cell->get("\\A"))) != 0) {
 			cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type);
-			replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->connections_["\\A"])));
+			replace_cell(module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->get("\\A"))));
 			goto next_cell;
 		}
 
-		if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->connections_["\\S"])) != 0) {
+		if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->get("\\S"))) != 0) {
 			cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type);
-			RTLIL::SigSpec tmp = cell->connections_["\\A"];
+			RTLIL::SigSpec tmp = cell->get("\\A");
-			cell->connections_["\\A"] = cell->connections_["\\B"];
+			cell->set("\\A", cell->get("\\B"));
-			cell->connections_["\\B"] = tmp;
+			cell->set("\\B", tmp);
-			cell->connections_["\\S"] = invert_map.at(assign_map(cell->connections_["\\S"]));
+			cell->set("\\S", invert_map.at(assign_map(cell->get("\\S"))));
 			OPT_DID_SOMETHING = true;
 			did_something = true;
 			goto next_cell;
 		}
 
 		if (cell->type == "$_INV_") {
-			RTLIL::SigSpec input = cell->connections_["\\A"];
+			RTLIL::SigSpec input = cell->get("\\A");
 			assign_map.apply(input);
 			if (input.match("1")) ACTION_DO_Y(0);
 			if (input.match("0")) ACTION_DO_Y(1);
@@ -375,8 +375,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$_AND_") {
 			RTLIL::SigSpec input;
-			input.append(cell->connections_["\\B"]);
+			input.append(cell->get("\\B"));
-			input.append(cell->connections_["\\A"]);
+			input.append(cell->get("\\A"));
 			assign_map.apply(input);
 			if (input.match(" 0")) ACTION_DO_Y(0);
 			if (input.match("0 ")) ACTION_DO_Y(0);
@@ -394,8 +394,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$_OR_") {
 			RTLIL::SigSpec input;
-			input.append(cell->connections_["\\B"]);
+			input.append(cell->get("\\B"));
-			input.append(cell->connections_["\\A"]);
+			input.append(cell->get("\\A"));
 			assign_map.apply(input);
 			if (input.match(" 1")) ACTION_DO_Y(1);
 			if (input.match("1 ")) ACTION_DO_Y(1);
@@ -413,8 +413,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$_XOR_") {
 			RTLIL::SigSpec input;
-			input.append(cell->connections_["\\B"]);
+			input.append(cell->get("\\B"));
-			input.append(cell->connections_["\\A"]);
+			input.append(cell->get("\\A"));
 			assign_map.apply(input);
 			if (input.match("00")) ACTION_DO_Y(0);
 			if (input.match("01")) ACTION_DO_Y(1);
@@ -428,9 +428,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$_MUX_") {
 			RTLIL::SigSpec input;
-			input.append(cell->connections_["\\S"]);
+			input.append(cell->get("\\S"));
-			input.append(cell->connections_["\\B"]);
+			input.append(cell->get("\\B"));
-			input.append(cell->connections_["\\A"]);
+			input.append(cell->get("\\A"));
 			assign_map.apply(input);
 			if (input.extract(2, 1) == input.extract(1, 1))
 				ACTION_DO("\\Y", input.extract(2, 1));
@@ -440,9 +440,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			if (input.match("10 ")) {
 				cover("opt.opt_const.mux_to_inv");
 				cell->type = "$_INV_";
-				cell->connections_["\\A"] = input.extract(0, 1);
+				cell->set("\\A", input.extract(0, 1));
-				cell->connections_.erase("\\B");
+				cell->unset("\\B");
-				cell->connections_.erase("\\S");
+				cell->unset("\\S");
 				goto next_cell;
 			}
 			if (input.match("11 ")) ACTION_DO_Y(1);
@@ -459,8 +459,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex")
 		{
-			RTLIL::SigSpec a = cell->connections_["\\A"];
+			RTLIL::SigSpec a = cell->get("\\A");
-			RTLIL::SigSpec b = cell->connections_["\\B"];
+			RTLIL::SigSpec b = cell->get("\\B");
 
 			if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
 				int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
@@ -495,8 +495,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (new_a.size() < a.size() || new_b.size() < b.size()) {
 				cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type);
-				cell->connections_["\\A"] = new_a;
+				cell->set("\\A", new_a);
-				cell->connections_["\\B"] = new_b;
+				cell->set("\\B", new_b);
 				cell->parameters["\\A_WIDTH"] = new_a.size();
 				cell->parameters["\\B_WIDTH"] = new_b.size();
 			}
@@ -505,24 +505,26 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 &&
 				cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1)
 		{
-			RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]);
+			RTLIL::SigSpec a = assign_map(cell->get("\\A"));
-			RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
+			RTLIL::SigSpec b = assign_map(cell->get("\\B"));
 
 			if (a.is_fully_const()) {
 				cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type);
-				std::swap(cell->connections_["\\A"], cell->connections_["\\B"]);
+				RTLIL::SigSpec tmp = cell->get("\\A");
+				cell->set("\\A", cell->get("\\B"));
+				cell->set("\\B", tmp);
 			}
 
 			if (b.is_fully_const()) {
 				if (b.as_bool() == (cell->type == "$eq")) {
 					RTLIL::SigSpec input = b;
-					ACTION_DO("\\Y", cell->connections_["\\A"]);
+					ACTION_DO("\\Y", cell->get("\\A"));
 				} else {
 					cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type);
 					cell->type = "$not";
 					cell->parameters.erase("\\B_WIDTH");
 					cell->parameters.erase("\\B_SIGNED");
-					cell->connections_.erase("\\B");
+					cell->unset("\\B");
 				}
 				goto next_cell;
 			}
@@ -536,8 +538,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$or" || cell->type == "$xor")
 			{
-				RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]);
+				RTLIL::SigSpec a = assign_map(cell->get("\\A"));
-				RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
+				RTLIL::SigSpec b = assign_map(cell->get("\\B"));
 
 				if (cell->type != "$sub" && a.is_fully_const() && a.as_bool() == false)
 					identity_wrt_b = true;
@@ -548,7 +550,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr")
 			{
-				RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
+				RTLIL::SigSpec b = assign_map(cell->get("\\B"));
 
 				if (b.is_fully_const() && b.as_bool() == false)
 					identity_wrt_a = true, identity_bu0 = true;
@@ -556,8 +558,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$mul")
 			{
-				RTLIL::SigSpec a = assign_map(cell->connections_["\\A"]);
+				RTLIL::SigSpec a = assign_map(cell->get("\\A"));
-				RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
+				RTLIL::SigSpec b = assign_map(cell->get("\\B"));
 
 				if (a.is_fully_const() && a.size() <= 32 && a.as_int() == 1)
 					identity_wrt_b = true;
@@ -568,7 +570,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$div")
 			{
-				RTLIL::SigSpec b = assign_map(cell->connections_["\\B"]);
+				RTLIL::SigSpec b = assign_map(cell->get("\\B"));
 
 				if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1)
 					identity_wrt_a = true;
@@ -585,13 +587,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
 
 				if (!identity_wrt_a) {
-					cell->connections_.at("\\A") = cell->connections_.at("\\B");
+					cell->set("\\A", cell->get("\\B"));
 					cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH");
 					cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED");
 				}
 
 				cell->type = identity_bu0 ? "$bu0" : "$pos";
-				cell->connections_.erase("\\B");
+				cell->unset("\\B");
 				cell->parameters.erase("\\B_WIDTH");
 				cell->parameters.erase("\\B_SIGNED");
 				cell->check();
@@ -603,18 +605,18 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		}
 
 		if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
-				cell->connections_["\\A"] == RTLIL::SigSpec(0, 1) && cell->connections_["\\B"] == RTLIL::SigSpec(1, 1)) {
+				cell->get("\\A") == RTLIL::SigSpec(0, 1) && cell->get("\\B") == RTLIL::SigSpec(1, 1)) {
 			cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type);
-			replace_cell(module, cell, "mux_bool", "\\Y", cell->connections_["\\S"]);
+			replace_cell(module, cell, "mux_bool", "\\Y", cell->get("\\S"));
 			goto next_cell;
 		}
 
 		if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
-				cell->connections_["\\A"] == RTLIL::SigSpec(1, 1) && cell->connections_["\\B"] == RTLIL::SigSpec(0, 1)) {
+				cell->get("\\A") == RTLIL::SigSpec(1, 1) && cell->get("\\B") == RTLIL::SigSpec(0, 1)) {
 			cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type);
-			cell->connections_["\\A"] = cell->connections_["\\S"];
+			cell->set("\\A", cell->get("\\S"));
-			cell->connections_.erase("\\B");
+			cell->unset("\\B");
-			cell->connections_.erase("\\S");
+			cell->unset("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -628,10 +630,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			goto next_cell;
 		}
 
-		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections_["\\A"] == RTLIL::SigSpec(0, 1)) {
+		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\A") == RTLIL::SigSpec(0, 1)) {
 			cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type);
-			cell->connections_["\\A"] = cell->connections_["\\S"];
+			cell->set("\\A", cell->get("\\S"));
-			cell->connections_.erase("\\S");
+			cell->unset("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -647,10 +649,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			goto next_cell;
 		}
 
-		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->connections_["\\B"] == RTLIL::SigSpec(1, 1)) {
+		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\B") == RTLIL::SigSpec(1, 1)) {
 			cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type);
-			cell->connections_["\\B"] = cell->connections_["\\S"];
+			cell->set("\\B", cell->get("\\S"));
-			cell->connections_.erase("\\S");
+			cell->unset("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -668,22 +670,22 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) {
 			RTLIL::SigSpec new_a, new_b, new_s;
-			int width = cell->connections_.at("\\A").size();
+			int width = cell->get("\\A").size();
-			if ((cell->connections_.at("\\A").is_fully_undef() && cell->connections_.at("\\B").is_fully_undef()) ||
+			if ((cell->get("\\A").is_fully_undef() && cell->get("\\B").is_fully_undef()) ||
-					cell->connections_.at("\\S").is_fully_undef()) {
+					cell->get("\\S").is_fully_undef()) {
 				cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type);
-				replace_cell(module, cell, "mux_undef", "\\Y", cell->connections_.at("\\A"));
+				replace_cell(module, cell, "mux_undef", "\\Y", cell->get("\\A"));
 				goto next_cell;
 			}
-			for (int i = 0; i < cell->connections_.at("\\S").size(); i++) {
+			for (int i = 0; i < cell->get("\\S").size(); i++) {
-				RTLIL::SigSpec old_b = cell->connections_.at("\\B").extract(i*width, width);
+				RTLIL::SigSpec old_b = cell->get("\\B").extract(i*width, width);
-				RTLIL::SigSpec old_s = cell->connections_.at("\\S").extract(i, 1);
+				RTLIL::SigSpec old_s = cell->get("\\S").extract(i, 1);
 				if (old_b.is_fully_undef() || old_s.is_fully_undef())
 					continue;
 				new_b.append(old_b);
 				new_s.append(old_s);
 			}
-			new_a = cell->connections_.at("\\A");
+			new_a = cell->get("\\A");
 			if (new_a.is_fully_undef() && new_s.size() > 0) {
 				new_a = new_b.extract((new_s.size()-1)*width, width);
 				new_b = new_b.extract(0, (new_s.size()-1)*width);
@@ -699,11 +701,11 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 				replace_cell(module, cell, "mux_sel01", "\\Y", new_s);
 				goto next_cell;
 			}
-			if (cell->connections_.at("\\S").size() != new_s.size()) {
+			if (cell->get("\\S").size() != new_s.size()) {
 				cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type);
-				cell->connections_.at("\\A") = new_a;
+				cell->set("\\A", new_a);
-				cell->connections_.at("\\B") = new_b;
+				cell->set("\\B", new_b);
-				cell->connections_.at("\\S") = new_s;
+				cell->set("\\S", new_s);
 				if (new_s.size() > 1) {
 					cell->type = "$pmux";
 					cell->parameters["\\S_WIDTH"] = new_s.size();
@@ -718,7 +720,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 #define FOLD_1ARG_CELL(_t) \
 		if (cell->type == "$" #_t) { \
-			RTLIL::SigSpec a = cell->connections_["\\A"]; \
+			RTLIL::SigSpec a = cell->get("\\A"); \
 			assign_map.apply(a); \
 			if (a.is_fully_const()) { \
 				RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
@@ -732,8 +734,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		}
 #define FOLD_2ARG_CELL(_t) \
 		if (cell->type == "$" #_t) { \
-			RTLIL::SigSpec a = cell->connections_["\\A"]; \
+			RTLIL::SigSpec a = cell->get("\\A"); \
-			RTLIL::SigSpec b = cell->connections_["\\B"]; \
+			RTLIL::SigSpec b = cell->get("\\B"); \
 			assign_map.apply(a), assign_map.apply(b); \
 			if (a.is_fully_const() && b.is_fully_const()) { \
 				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \
@@ -787,13 +789,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		// be very conservative with optimizing $mux cells as we do not want to break mux trees
 		if (cell->type == "$mux") {
-			RTLIL::SigSpec input = assign_map(cell->connections_["\\S"]);
+			RTLIL::SigSpec input = assign_map(cell->get("\\S"));
-			RTLIL::SigSpec inA = assign_map(cell->connections_["\\A"]);
+			RTLIL::SigSpec inA = assign_map(cell->get("\\A"));
-			RTLIL::SigSpec inB = assign_map(cell->connections_["\\B"]);
+			RTLIL::SigSpec inB = assign_map(cell->get("\\B"));
 			if (input.is_fully_const())
-				ACTION_DO("\\Y", input.as_bool() ? cell->connections_["\\B"] : cell->connections_["\\A"]);
+				ACTION_DO("\\Y", input.as_bool() ? cell->get("\\B") : cell->get("\\A"));
 			else if (inA == inB)
-				ACTION_DO("\\Y", cell->connections_["\\A"]);
+				ACTION_DO("\\Y", cell->get("\\A"));
 		}
 
 		if (!keepdc && cell->type == "$mul")
@@ -802,9 +804,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			bool b_signed = cell->parameters["\\B_SIGNED"].as_bool();
 			bool swapped_ab = false;
 
-			RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]);
+			RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-			RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]);
+			RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
-			RTLIL::SigSpec sig_y = assign_map(cell->connections_["\\Y"]);
+			RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y"));
 
 			if (sig_b.is_fully_const() && sig_b.size() <= 32)
 				std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true;
@@ -820,7 +822,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					log("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n",
 							cell->name.c_str(), module->name.c_str());
 
-					module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+					module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
 					module->remove(cell);
 
 					OPT_DID_SOMETHING = true;
@@ -840,7 +842,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 								a_val, cell->name.c_str(), module->name.c_str(), i);
 
 						if (!swapped_ab) {
-							cell->connections_["\\A"] = cell->connections_["\\B"];
+							cell->set("\\A", cell->get("\\B"));
 							cell->parameters["\\A_WIDTH"] = cell->parameters["\\B_WIDTH"];
 							cell->parameters["\\A_SIGNED"] = cell->parameters["\\B_SIGNED"];
 						}
@@ -853,7 +855,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 						cell->type = "$shl";
 						cell->parameters["\\B_WIDTH"] = SIZE(new_b);
 						cell->parameters["\\B_SIGNED"] = false;
-						cell->connections_["\\B"] = new_b;
+						cell->set("\\B", new_b);
 						cell->check();
 
 						OPT_DID_SOMETHING = true;

passes/opt/opt_muxtree.cc

@@ -88,10 +88,10 @@ struct OptMuxtreeWorker
 			RTLIL::Cell *cell = cell_it.second;
 			if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
 			{
-				RTLIL::SigSpec sig_a = cell->connections_["\\A"];
+				RTLIL::SigSpec sig_a = cell->get("\\A");
-				RTLIL::SigSpec sig_b = cell->connections_["\\B"];
+				RTLIL::SigSpec sig_b = cell->get("\\B");
-				RTLIL::SigSpec sig_s = cell->connections_["\\S"];
+				RTLIL::SigSpec sig_s = cell->get("\\S");
-				RTLIL::SigSpec sig_y = cell->connections_["\\Y"];
+				RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 				muxinfo_t muxinfo;
 				muxinfo.cell = cell;
@@ -130,7 +130,7 @@ struct OptMuxtreeWorker
 			}
 			else
 			{
-				for (auto &it : cell->connections_) {
+				for (auto &it : cell->connections()) {
 					for (int idx : sig2bits(it.second))
 						bit2info[idx].seen_non_mux = true;
 				}
@@ -194,10 +194,10 @@ struct OptMuxtreeWorker
 				continue;
 			}
 
-			RTLIL::SigSpec sig_a = mi.cell->connections_["\\A"];
+			RTLIL::SigSpec sig_a = mi.cell->get("\\A");
-			RTLIL::SigSpec sig_b = mi.cell->connections_["\\B"];
+			RTLIL::SigSpec sig_b = mi.cell->get("\\B");
-			RTLIL::SigSpec sig_s = mi.cell->connections_["\\S"];
+			RTLIL::SigSpec sig_s = mi.cell->get("\\S");
-			RTLIL::SigSpec sig_y = mi.cell->connections_["\\Y"];
+			RTLIL::SigSpec sig_y = mi.cell->get("\\Y");
 
 			RTLIL::SigSpec sig_ports = sig_b;
 			sig_ports.append(sig_a);
@@ -205,7 +205,7 @@ struct OptMuxtreeWorker
 			if (live_ports.size() == 1)
 			{
 				RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.size(), sig_a.size());
-				module->connections_.push_back(RTLIL::SigSig(sig_y, sig_in));
+				module->connect(RTLIL::SigSig(sig_y, sig_in));
 				module->remove(mi.cell);
 			}
 			else
@@ -222,9 +222,9 @@ struct OptMuxtreeWorker
 					}
 				}
 
-				mi.cell->connections_["\\A"] = new_sig_a;
+				mi.cell->set("\\A", new_sig_a);
-				mi.cell->connections_["\\B"] = new_sig_b;
+				mi.cell->set("\\B", new_sig_b);
-				mi.cell->connections_["\\S"] = new_sig_s;
+				mi.cell->set("\\S", new_sig_s);
 				if (new_sig_s.size() == 1) {
 					mi.cell->type = "$mux";
 					mi.cell->parameters.erase("\\S_WIDTH");

passes/opt/opt_reduce.cc

@@ -43,7 +43,7 @@ struct OptReduceWorker
 			return;
 		cells.erase(cell);
 
-		RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]);
+		RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
 		std::set<RTLIL::SigBit> new_sig_a_bits;
 
 		for (auto &bit : sig_a.to_sigbit_set())
@@ -73,8 +73,8 @@ struct OptReduceWorker
 			for (auto child_cell : drivers.find(bit)) {
 				if (child_cell->type == cell->type) {
 					opt_reduce(cells, drivers, child_cell);
-					if (child_cell->connections_["\\Y"][0] == bit) {
+					if (child_cell->get("\\Y")[0] == bit) {
-						std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->connections_["\\A"]).to_sigbit_set();
+						std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->get("\\A")).to_sigbit_set();
 						new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end());
 					} else
 						new_sig_a_bits.insert(RTLIL::State::S0);
@@ -87,23 +87,23 @@ struct OptReduceWorker
 
 		RTLIL::SigSpec new_sig_a(new_sig_a_bits);
 
-		if (new_sig_a != sig_a || sig_a.size() != cell->connections_["\\A"].size()) {
+		if (new_sig_a != sig_a || sig_a.size() != cell->get("\\A").size()) {
 			log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
 			did_something = true;
 			OPT_DID_SOMETHING = true;
 			total_count++;
 		}
 
-		cell->connections_["\\A"] = new_sig_a;
+		cell->set("\\A", new_sig_a);
 		cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size());
 		return;
 	}
 
 	void opt_mux(RTLIL::Cell *cell)
 	{
-		RTLIL::SigSpec sig_a = assign_map(cell->connections_["\\A"]);
+		RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-		RTLIL::SigSpec sig_b = assign_map(cell->connections_["\\B"]);
+		RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
-		RTLIL::SigSpec sig_s = assign_map(cell->connections_["\\S"]);
+		RTLIL::SigSpec sig_s = assign_map(cell->get("\\S"));
 
 		RTLIL::SigSpec new_sig_b, new_sig_s;
 		std::set<RTLIL::SigSpec> handled_sig;
@@ -125,14 +125,14 @@ struct OptReduceWorker
 			if (this_s.size() > 1)
 			{
 				RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, "$reduce_or");
-				reduce_or_cell->connections_["\\A"] = this_s;
+				reduce_or_cell->set("\\A", this_s);
 				reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 				reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size());
 				reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 
 				RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
 				this_s = RTLIL::SigSpec(reduce_or_wire);
-				reduce_or_cell->connections_["\\Y"] = this_s;
+				reduce_or_cell->set("\\Y", this_s);
 			}
 
 			new_sig_b.append(this_b);
@@ -149,14 +149,14 @@ struct OptReduceWorker
 
 		if (new_sig_s.size() == 0)
 		{
-			module->connections_.push_back(RTLIL::SigSig(cell->connections_["\\Y"], cell->connections_["\\A"]));
+			module->connect(RTLIL::SigSig(cell->get("\\Y"), cell->get("\\A")));
-			assign_map.add(cell->connections_["\\Y"], cell->connections_["\\A"]);
+			assign_map.add(cell->get("\\Y"), cell->get("\\A"));
 			module->remove(cell);
 		}
 		else
 		{
-			cell->connections_["\\B"] = new_sig_b;
+			cell->set("\\B", new_sig_b);
-			cell->connections_["\\S"] = new_sig_s;
+			cell->set("\\S", new_sig_s);
 			if (new_sig_s.size() > 1) {
 				cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size());
 			} else {
@@ -168,9 +168,9 @@ struct OptReduceWorker
 
 	void opt_mux_bits(RTLIL::Cell *cell)
 	{
-		std::vector<RTLIL::SigBit> sig_a = assign_map(cell->connections_["\\A"]).to_sigbit_vector();
+		std::vector<RTLIL::SigBit> sig_a = assign_map(cell->get("\\A")).to_sigbit_vector();
-		std::vector<RTLIL::SigBit> sig_b = assign_map(cell->connections_["\\B"]).to_sigbit_vector();
+		std::vector<RTLIL::SigBit> sig_b = assign_map(cell->get("\\B")).to_sigbit_vector();
-		std::vector<RTLIL::SigBit> sig_y = assign_map(cell->connections_["\\Y"]).to_sigbit_vector();
+		std::vector<RTLIL::SigBit> sig_y = assign_map(cell->get("\\Y")).to_sigbit_vector();
 
 		std::vector<RTLIL::SigBit> new_sig_y;
 		RTLIL::SigSig old_sig_conn;
@@ -211,26 +211,32 @@ struct OptReduceWorker
 		if (new_sig_y.size() != sig_y.size())
 		{
 			log("    Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
-			log("      Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections_["\\A"]),
+			log("      Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->get("\\A")),
-					log_signal(cell->connections_["\\B"]), log_signal(cell->connections_["\\Y"]));
+					log_signal(cell->get("\\B")), log_signal(cell->get("\\Y")));
 
-			cell->connections_["\\A"] = RTLIL::SigSpec();
+			cell->set("\\A", RTLIL::SigSpec());
-			for (auto &in_tuple : consolidated_in_tuples)
+			for (auto &in_tuple : consolidated_in_tuples) {
-				cell->connections_["\\A"].append(in_tuple.at(0));
+				RTLIL::SigSpec new_a = cell->get("\\A");
+				new_a.append(in_tuple.at(0));
+				cell->set("\\A", new_a);
+			}
 
-			cell->connections_["\\B"] = RTLIL::SigSpec();
+			cell->set("\\B", RTLIL::SigSpec());
-			for (int i = 1; i <= cell->connections_["\\S"].size(); i++)
+			for (int i = 1; i <= cell->get("\\S").size(); i++)
-				for (auto &in_tuple : consolidated_in_tuples)
+				for (auto &in_tuple : consolidated_in_tuples) {
-					cell->connections_["\\B"].append(in_tuple.at(i));
+					RTLIL::SigSpec new_b = cell->get("\\B");
+					new_b.append(in_tuple.at(i));
+					cell->set("\\B", new_b);
+				}
 
 			cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size());
-			cell->connections_["\\Y"] = new_sig_y;
+			cell->set("\\Y", new_sig_y);
 
-			log("      New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->connections_["\\A"]),
+			log("      New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->get("\\A")),
-					log_signal(cell->connections_["\\B"]), log_signal(cell->connections_["\\Y"]));
+					log_signal(cell->get("\\B")), log_signal(cell->get("\\Y")));
 			log("      New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
 
-			module->connections_.push_back(old_sig_conn);
+			module->connect(old_sig_conn);
 			module->check();
 
 			did_something = true;
@@ -251,14 +257,14 @@ struct OptReduceWorker
 		for (auto &cell_it : module->cells) {
 			RTLIL::Cell *cell = cell_it.second;
 			if (cell->type == "$mem")
-				mem_wren_sigs.add(assign_map(cell->connections_["\\WR_EN"]));
+				mem_wren_sigs.add(assign_map(cell->get("\\WR_EN")));
 			if (cell->type == "$memwr")
-				mem_wren_sigs.add(assign_map(cell->connections_["\\EN"]));
+				mem_wren_sigs.add(assign_map(cell->get("\\EN")));
 		}
 		for (auto &cell_it : module->cells) {
 			RTLIL::Cell *cell = cell_it.second;
-			if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->connections_["\\Q"])))
+			if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->get("\\Q"))))
-				mem_wren_sigs.add(assign_map(cell->connections_["\\D"]));
+				mem_wren_sigs.add(assign_map(cell->get("\\D")));
 		}
 
 		bool keep_expanding_mem_wren_sigs = true;
@@ -266,12 +272,12 @@ struct OptReduceWorker
 			keep_expanding_mem_wren_sigs = false;
 			for (auto &cell_it : module->cells) {
 				RTLIL::Cell *cell = cell_it.second;
-				if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->connections_["\\Y"]))) {
+				if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->get("\\Y")))) {
-					if (!mem_wren_sigs.check_all(assign_map(cell->connections_["\\A"])) ||
+					if (!mem_wren_sigs.check_all(assign_map(cell->get("\\A"))) ||
-							!mem_wren_sigs.check_all(assign_map(cell->connections_["\\B"])))
+							!mem_wren_sigs.check_all(assign_map(cell->get("\\B"))))
 						keep_expanding_mem_wren_sigs = true;
-					mem_wren_sigs.add(assign_map(cell->connections_["\\A"]));
+					mem_wren_sigs.add(assign_map(cell->get("\\A")));
-					mem_wren_sigs.add(assign_map(cell->connections_["\\B"]));
+					mem_wren_sigs.add(assign_map(cell->get("\\B")));
 				}
 			}
 		}
@@ -293,7 +299,7 @@ struct OptReduceWorker
 					RTLIL::Cell *cell = cell_it.second;
 					if (cell->type != type || !design->selected(module, cell))
 						continue;
-					drivers.insert(assign_map(cell->connections_["\\Y"]), cell);
+					drivers.insert(assign_map(cell->get("\\Y")), cell);
 					cells.insert(cell);
 				}
 
@@ -315,7 +321,7 @@ struct OptReduceWorker
 			{
 				// this optimization is to aggressive for most coarse-grain applications.
 				// but we always want it for multiplexers driving write enable ports.
-				if (do_fine || mem_wren_sigs.check_any(assign_map(cell->connections_.at("\\Y"))))
+				if (do_fine || mem_wren_sigs.check_any(assign_map(cell->get("\\Y"))))
 					opt_mux_bits(cell);
 
 				opt_mux(cell);

passes/opt/opt_rmdff.cc

@@ -33,34 +33,34 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 	RTLIL::Const val_cp, val_rp, val_rv;
 
 	if (dff->type == "$_DFF_N_" || dff->type == "$_DFF_P_") {
-		sig_d = dff->connections_["\\D"];
+		sig_d = dff->get("\\D");
-		sig_q = dff->connections_["\\Q"];
+		sig_q = dff->get("\\Q");
-		sig_c = dff->connections_["\\C"];
+		sig_c = dff->get("\\C");
 		val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1);
 	}
 	else if (dff->type.substr(0,6) == "$_DFF_" && dff->type.substr(9) == "_" &&
 			(dff->type[6] == 'N' || dff->type[6] == 'P') &&
 			(dff->type[7] == 'N' || dff->type[7] == 'P') &&
 			(dff->type[8] == '0' || dff->type[8] == '1')) {
-		sig_d = dff->connections_["\\D"];
+		sig_d = dff->get("\\D");
-		sig_q = dff->connections_["\\Q"];
+		sig_q = dff->get("\\Q");
-		sig_c = dff->connections_["\\C"];
+		sig_c = dff->get("\\C");
-		sig_r = dff->connections_["\\R"];
+		sig_r = dff->get("\\R");
 		val_cp = RTLIL::Const(dff->type[6] == 'P', 1);
 		val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
 		val_rv = RTLIL::Const(dff->type[8] == '1', 1);
 	}
 	else if (dff->type == "$dff") {
-		sig_d = dff->connections_["\\D"];
+		sig_d = dff->get("\\D");
-		sig_q = dff->connections_["\\Q"];
+		sig_q = dff->get("\\Q");
-		sig_c = dff->connections_["\\CLK"];
+		sig_c = dff->get("\\CLK");
 		val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
 	}
 	else if (dff->type == "$adff") {
-		sig_d = dff->connections_["\\D"];
+		sig_d = dff->get("\\D");
-		sig_q = dff->connections_["\\Q"];
+		sig_q = dff->get("\\Q");
-		sig_c = dff->connections_["\\CLK"];
+		sig_c = dff->get("\\CLK");
-		sig_r = dff->connections_["\\ARST"];
+		sig_r = dff->get("\\ARST");
 		val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
 		val_rp = RTLIL::Const(dff->parameters["\\ARST_POLARITY"].as_bool(), 1);
 		val_rv = dff->parameters["\\ARST_VALUE"];
@@ -85,16 +85,16 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		std::set<RTLIL::Cell*> muxes;
 		mux_drivers.find(sig_d, muxes);
 		for (auto mux : muxes) {
-			RTLIL::SigSpec sig_a = assign_map(mux->connections_.at("\\A"));
+			RTLIL::SigSpec sig_a = assign_map(mux->get("\\A"));
-			RTLIL::SigSpec sig_b = assign_map(mux->connections_.at("\\B"));
+			RTLIL::SigSpec sig_b = assign_map(mux->get("\\B"));
 			if (sig_a == sig_q && sig_b.is_fully_const()) {
 				RTLIL::SigSig conn(sig_q, sig_b);
-				mod->connections_.push_back(conn);
+				mod->connect(conn);
 				goto delete_dff;
 			}
 			if (sig_b == sig_q && sig_a.is_fully_const()) {
 				RTLIL::SigSig conn(sig_q, sig_a);
-				mod->connections_.push_back(conn);
+				mod->connect(conn);
 				goto delete_dff;
 			}
 		}
@@ -104,36 +104,36 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		if (val_rv.bits.size() == 0)
 			val_rv = val_init;
 		RTLIL::SigSig conn(sig_q, val_rv);
-		mod->connections_.push_back(conn);
+		mod->connect(conn);
 		goto delete_dff;
 	}
 
 	if (sig_d.is_fully_undef() && sig_r.size() && !has_init) {
 		RTLIL::SigSig conn(sig_q, val_rv);
-		mod->connections_.push_back(conn);
+		mod->connect(conn);
 		goto delete_dff;
 	}
 
 	if (sig_d.is_fully_undef() && !sig_r.size() && has_init) {
 		RTLIL::SigSig conn(sig_q, val_init);
-		mod->connections_.push_back(conn);
+		mod->connect(conn);
 		goto delete_dff;
 	}
 
 	if (sig_d.is_fully_const() && !sig_r.size() && !has_init) {
 		RTLIL::SigSig conn(sig_q, sig_d);
-		mod->connections_.push_back(conn);
+		mod->connect(conn);
 		goto delete_dff;
 	}
 
 	if (sig_d == sig_q && !(sig_r.size() && has_init)) {
 		if (sig_r.size()) {
 			RTLIL::SigSig conn(sig_q, val_rv);
-			mod->connections_.push_back(conn);
+			mod->connect(conn);
 		}
 		if (has_init) {
 			RTLIL::SigSig conn(sig_q, val_init);
-			mod->connections_.push_back(conn);
+			mod->connect(conn);
 		}
 		goto delete_dff;
 	}
@@ -181,8 +181,8 @@ struct OptRmdffPass : public Pass {
 			std::vector<std::string> dff_list;
 			for (auto &it : mod_it.second->cells) {
 				if (it.second->type == "$mux" || it.second->type == "$pmux") {
-					if (it.second->connections_.at("\\A").size() == it.second->connections_.at("\\B").size())
+					if (it.second->get("\\A").size() == it.second->get("\\B").size())
-						mux_drivers.insert(assign_map(it.second->connections_.at("\\Y")), it.second);
+						mux_drivers.insert(assign_map(it.second->get("\\Y")), it.second);
 					continue;
 				}
 				if (!design->selected(mod_it.second, it.second))

passes/opt/opt_share.cc

@@ -66,7 +66,7 @@ struct OptShareWorker
 		for (auto &it : cell->parameters)
 			hash_string += "P " + it.first + "=" + it.second.as_string() + "\n";
 
-		const std::map<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections_;
+		const std::map<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
 		std::map<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
 
 		if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" ||
@@ -135,8 +135,8 @@ struct OptShareWorker
 			return true;
 		}
 
-		std::map<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections_;
+		std::map<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections();
-		std::map<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections_;
+		std::map<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections();
 
 		for (auto &it : conn1) {
 			if (ct.cell_output(cell1->type, it.first))
@@ -180,8 +180,8 @@ struct OptShareWorker
 		}
 
 		if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) {
-			std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->connections_.at("\\Q")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->get("\\Q")).to_sigbit_vector();
-			std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->connections_.at("\\Q")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->get("\\Q")).to_sigbit_vector();
 			for (size_t i = 0; i < q1.size(); i++)
 				if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
 					lt = q1.at(i) < q2.at(i);
@@ -261,12 +261,12 @@ struct OptShareWorker
 				if (sharemap.count(cell) > 0) {
 					did_something = true;
 					log("  Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
-					for (auto &it : cell->connections_) {
+					for (auto &it : cell->connections()) {
 						if (ct.cell_output(cell->type, it.first)) {
-							RTLIL::SigSpec other_sig = sharemap[cell]->connections_[it.first];
+							RTLIL::SigSpec other_sig = sharemap[cell]->get(it.first);
 							log("    Redirecting output %s: %s = %s\n", it.first.c_str(),
 									log_signal(it.second), log_signal(other_sig));
-							module->connections_.push_back(RTLIL::SigSig(it.second, other_sig));
+							module->connect(RTLIL::SigSig(it.second, other_sig));
 							assign_map.add(it.second, other_sig);
 						}
 					}

passes/proc/proc_arst.cc

@@ -35,40 +35,40 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
 
 	for (auto &cell_it : mod->cells) {
 		RTLIL::Cell *cell = cell_it.second;
-		if (cell->type == "$reduce_or" && cell->connections_["\\Y"] == signal)
+		if (cell->type == "$reduce_or" && cell->get("\\Y") == signal)
-			return check_signal(mod, cell->connections_["\\A"], ref, polarity);
+			return check_signal(mod, cell->get("\\A"), ref, polarity);
-		if (cell->type == "$reduce_bool" && cell->connections_["\\Y"] == signal)
+		if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal)
-			return check_signal(mod, cell->connections_["\\A"], ref, polarity);
+			return check_signal(mod, cell->get("\\A"), ref, polarity);
-		if (cell->type == "$logic_not" && cell->connections_["\\Y"] == signal) {
+		if (cell->type == "$logic_not" && cell->get("\\Y") == signal) {
 			polarity = !polarity;
-			return check_signal(mod, cell->connections_["\\A"], ref, polarity);
+			return check_signal(mod, cell->get("\\A"), ref, polarity);
 		}
-		if (cell->type == "$not" && cell->connections_["\\Y"] == signal) {
+		if (cell->type == "$not" && cell->get("\\Y") == signal) {
 			polarity = !polarity;
-			return check_signal(mod, cell->connections_["\\A"], ref, polarity);
+			return check_signal(mod, cell->get("\\A"), ref, polarity);
 		}
-		if ((cell->type == "$eq" || cell->type == "$eqx") && cell->connections_["\\Y"] == signal) {
+		if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) {
-			if (cell->connections_["\\A"].is_fully_const()) {
+			if (cell->get("\\A").is_fully_const()) {
-				if (!cell->connections_["\\A"].as_bool())
+				if (!cell->get("\\A").as_bool())
 					polarity = !polarity;
-				return check_signal(mod, cell->connections_["\\B"], ref, polarity);
+				return check_signal(mod, cell->get("\\B"), ref, polarity);
 			}
-			if (cell->connections_["\\B"].is_fully_const()) {
+			if (cell->get("\\B").is_fully_const()) {
-				if (!cell->connections_["\\B"].as_bool())
+				if (!cell->get("\\B").as_bool())
 					polarity = !polarity;
-				return check_signal(mod, cell->connections_["\\A"], ref, polarity);
+				return check_signal(mod, cell->get("\\A"), ref, polarity);
 			}
 		}
-		if ((cell->type == "$ne" || cell->type == "$nex") && cell->connections_["\\Y"] == signal) {
+		if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) {
-			if (cell->connections_["\\A"].is_fully_const()) {
+			if (cell->get("\\A").is_fully_const()) {
-				if (cell->connections_["\\A"].as_bool())
+				if (cell->get("\\A").as_bool())
 					polarity = !polarity;
-				return check_signal(mod, cell->connections_["\\B"], ref, polarity);
+				return check_signal(mod, cell->get("\\B"), ref, polarity);
 			}
-			if (cell->connections_["\\B"].is_fully_const()) {
+			if (cell->get("\\B").is_fully_const()) {
-				if (cell->connections_["\\B"].as_bool())
+				if (cell->get("\\B").as_bool())
 					polarity = !polarity;
-				return check_signal(mod, cell->connections_["\\A"], ref, polarity);
+				return check_signal(mod, cell->get("\\A"), ref, polarity);
 			}
 		}
 	}

passes/proc/proc_dff.cc

@@ -77,8 +77,8 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
 			cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 			cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
 			cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-			cell->connections_["\\A"] = sync_low_signals;
+			cell->set("\\A", sync_low_signals);
-			cell->connections_["\\Y"] = sync_low_signals = mod->addWire(NEW_ID);
+			cell->set("\\Y", sync_low_signals = mod->addWire(NEW_ID));
 		}
 
 		if (sync_low_signals.size() > 0) {
@@ -86,9 +86,9 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
 			cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 			cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
 			cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-			cell->connections_["\\A"] = sync_low_signals;
+			cell->set("\\A", sync_low_signals);
-			cell->connections_["\\Y"] = mod->addWire(NEW_ID);
+			cell->set("\\Y", mod->addWire(NEW_ID));
-			sync_high_signals.append(cell->connections_["\\Y"]);
+			sync_high_signals.append(cell->get("\\Y"));
 		}
 
 		if (sync_high_signals.size() > 1) {
@@ -96,30 +96,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
 			cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 			cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size());
 			cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-			cell->connections_["\\A"] = sync_high_signals;
+			cell->set("\\A", sync_high_signals);
-			cell->connections_["\\Y"] = sync_high_signals = mod->addWire(NEW_ID);
+			cell->set("\\Y", sync_high_signals = mod->addWire(NEW_ID));
 		}
 
 		RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not");
 		inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 		inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size());
 		inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size());
-		inv_cell->connections_["\\A"] = sync_value;
+		inv_cell->set("\\A", sync_value);
-		inv_cell->connections_["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size());
+		inv_cell->set("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
 
 		RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux");
 		mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
-		mux_set_cell->connections_["\\A"] = sig_sr_set;
+		mux_set_cell->set("\\A", sig_sr_set);
-		mux_set_cell->connections_["\\B"] = sync_value;
+		mux_set_cell->set("\\B", sync_value);
-		mux_set_cell->connections_["\\S"] = sync_high_signals;
+		mux_set_cell->set("\\S", sync_high_signals);
-		mux_set_cell->connections_["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size());
+		mux_set_cell->set("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
 
 		RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux");
 		mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
-		mux_clr_cell->connections_["\\A"] = sig_sr_clr;
+		mux_clr_cell->set("\\A", sig_sr_clr);
-		mux_clr_cell->connections_["\\B"] = sync_value_inv;
+		mux_clr_cell->set("\\B", sync_value_inv);
-		mux_clr_cell->connections_["\\S"] = sync_high_signals;
+		mux_clr_cell->set("\\S", sync_high_signals);
-		mux_clr_cell->connections_["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size());
+		mux_clr_cell->set("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
 	}
 
 	std::stringstream sstr;
@@ -131,11 +131,11 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
 	cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
 	cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
 	cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
-	cell->connections_["\\D"] = sig_d;
+	cell->set("\\D", sig_d);
-	cell->connections_["\\Q"] = sig_q;
+	cell->set("\\Q", sig_q);
-	cell->connections_["\\CLK"] = clk;
+	cell->set("\\CLK", clk);
-	cell->connections_["\\SET"] = sig_sr_set;
+	cell->set("\\SET", sig_sr_set);
-	cell->connections_["\\CLR"] = sig_sr_clr;
+	cell->set("\\CLR", sig_sr_clr);
 
 	log("  created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
 			cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
@@ -155,22 +155,22 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
 	inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 	inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size());
 	inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size());
-	inv_set->connections_["\\A"] = sig_set;
+	inv_set->set("\\A", sig_set);
-	inv_set->connections_["\\Y"] = sig_set_inv;
+	inv_set->set("\\Y", sig_set_inv);
 
 	RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux");
 	mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
-	mux_sr_set->connections_[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
+	mux_sr_set->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
-	mux_sr_set->connections_[set_polarity ? "\\B" : "\\A"] = sig_set;
+	mux_sr_set->set(set_polarity ? "\\B" : "\\A", sig_set);
-	mux_sr_set->connections_["\\Y"] = sig_sr_set;
+	mux_sr_set->set("\\Y", sig_sr_set);
-	mux_sr_set->connections_["\\S"] = set;
+	mux_sr_set->set("\\S", set);
 
 	RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux");
 	mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
-	mux_sr_clr->connections_[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
+	mux_sr_clr->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
-	mux_sr_clr->connections_[set_polarity ? "\\B" : "\\A"] = sig_set_inv;
+	mux_sr_clr->set(set_polarity ? "\\B" : "\\A", sig_set_inv);
-	mux_sr_clr->connections_["\\Y"] = sig_sr_clr;
+	mux_sr_clr->set("\\Y", sig_sr_clr);
-	mux_sr_clr->connections_["\\S"] = set;
+	mux_sr_clr->set("\\S", set);
 
 	RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
 	cell->attributes = proc->attributes;
@@ -178,11 +178,11 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
 	cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
 	cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
 	cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
-	cell->connections_["\\D"] = sig_in;
+	cell->set("\\D", sig_in);
-	cell->connections_["\\Q"] = sig_out;
+	cell->set("\\Q", sig_out);
-	cell->connections_["\\CLK"] = clk;
+	cell->set("\\CLK", clk);
-	cell->connections_["\\SET"] = sig_sr_set;
+	cell->set("\\SET", sig_sr_set);
-	cell->connections_["\\CLR"] = sig_sr_clr;
+	cell->set("\\CLR", sig_sr_clr);
 
 	log("  created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
 			clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
@@ -204,11 +204,11 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_
 	}
 	cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
 
-	cell->connections_["\\D"] = sig_in;
+	cell->set("\\D", sig_in);
-	cell->connections_["\\Q"] = sig_out;
+	cell->set("\\Q", sig_out);
 	if (arst)
-		cell->connections_["\\ARST"] = *arst;
+		cell->set("\\ARST", *arst);
-	cell->connections_["\\CLK"] = clk;
+	cell->set("\\CLK", clk);
 
 	log("  created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
 	if (arst)
@@ -296,9 +296,9 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 				cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size());
 				cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size());
 				cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-				cell->connections_["\\A"] = inputs;
+				cell->set("\\A", inputs);
-				cell->connections_["\\B"] = compare;
+				cell->set("\\B", compare);
-				cell->connections_["\\Y"] = sync_level->signal;
+				cell->set("\\Y", sync_level->signal);
 
 				many_async_rules.clear();
 			}
@@ -322,7 +322,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 			if (sync_edge || sync_level || many_async_rules.size() > 0)
 				log_error("Mixed always event with edge and/or level sensitive events!\n");
 			log("  created direct connection (no actual register cell created).\n");
-			mod->connections_.push_back(RTLIL::SigSig(sig, insig));
+			mod->connect(RTLIL::SigSig(sig, insig));
 			continue;
 		}
 

passes/proc/proc_mux.cc

@@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 
 		if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1))
 		{
-			mod->connections_.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig));
+			mod->connect(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig));
 		}
 		else
 		{
@@ -96,9 +96,9 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 			eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size());
 			eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 
-			eq_cell->connections_["\\A"] = sig;
+			eq_cell->set("\\A", sig);
-			eq_cell->connections_["\\B"] = comp;
+			eq_cell->set("\\B", comp);
-			eq_cell->connections_["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++);
+			eq_cell->set("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
 		}
 	}
 
@@ -122,8 +122,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 		any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);
 		any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 
-		any_cell->connections_["\\A"] = cmp_wire;
+		any_cell->set("\\A", cmp_wire);
-		any_cell->connections_["\\Y"] = RTLIL::SigSpec(ctrl_wire);
+		any_cell->set("\\Y", RTLIL::SigSpec(ctrl_wire));
 	}
 
 	return RTLIL::SigSpec(ctrl_wire);
@@ -157,10 +157,10 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 	mux_cell->attributes = sw->attributes;
 
 	mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
-	mux_cell->connections_["\\A"] = else_signal;
+	mux_cell->set("\\A", else_signal);
-	mux_cell->connections_["\\B"] = when_signal;
+	mux_cell->set("\\B", when_signal);
-	mux_cell->connections_["\\S"] = ctrl_sig;
+	mux_cell->set("\\S", ctrl_sig);
-	mux_cell->connections_["\\Y"] = RTLIL::SigSpec(result_wire);
+	mux_cell->set("\\Y", RTLIL::SigSpec(result_wire));
 
 	last_mux_cell = mux_cell;
 	return RTLIL::SigSpec(result_wire);
@@ -169,14 +169,21 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw)
 {
 	assert(last_mux_cell != NULL);
-	assert(when_signal.size() == last_mux_cell->connections_["\\A"].size());
+	assert(when_signal.size() == last_mux_cell->get("\\A").size());
 
 	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);
 	assert(ctrl_sig.size() == 1);
 	last_mux_cell->type = "$pmux";
-	last_mux_cell->connections_["\\S"].append(ctrl_sig);
+
-	last_mux_cell->connections_["\\B"].append(when_signal);
+	RTLIL::SigSpec new_s = last_mux_cell->get("\\S");
-	last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->connections_["\\S"].size();
+	new_s.append(ctrl_sig);
+	last_mux_cell->set("\\S", new_s);
+
+	RTLIL::SigSpec new_b = last_mux_cell->get("\\B");
+	new_b.append(when_signal);
+	last_mux_cell->set("\\B", new_b);
+
+	last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->get("\\S").size();
 }
 
 static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval)
@@ -256,7 +263,7 @@ static void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc)
 		log("  creating decoder for signal `%s'.\n", log_signal(sig));
 
 		RTLIL::SigSpec value = signal_to_mux_tree(mod, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size()));
-		mod->connections_.push_back(RTLIL::SigSig(sig, value));
+		mod->connect(RTLIL::SigSig(sig, value));
 	}
 }
 

passes/sat/expose.cc

@@ -83,8 +83,8 @@ static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *modu
 	SigPool dffsignals;
 
 	for (auto &it : module->cells) {
-		if (ct.cell_known(it.second->type) && it.second->connections_.count("\\Q"))
+		if (ct.cell_known(it.second->type) && it.second->connections().count("\\Q"))
-			dffsignals.add(sigmap(it.second->connections_.at("\\Q")));
+			dffsignals.add(sigmap(it.second->get("\\Q")));
 	}
 
 	for (auto &it : module->wires) {
@@ -113,10 +113,10 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
 		info.cell = it.second;
 
 		if (info.cell->type == "$dff") {
-			info.bit_clk = sigmap(info.cell->connections_.at("\\CLK")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit();
 			info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
-			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->connections_.at("\\D")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector();
-			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->connections_.at("\\Q")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector();
 			for (size_t i = 0; i < sig_d.size(); i++) {
 				info.bit_d = sig_d.at(i);
 				bit_info[sig_q.at(i)] = info;
@@ -125,12 +125,12 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
 		}
 
 		if (info.cell->type == "$adff") {
-			info.bit_clk = sigmap(info.cell->connections_.at("\\CLK")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit();
-			info.bit_arst = sigmap(info.cell->connections_.at("\\ARST")).to_single_sigbit();
+			info.bit_arst = sigmap(info.cell->get("\\ARST")).to_single_sigbit();
 			info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
 			info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool();
-			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->connections_.at("\\D")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector();
-			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->connections_.at("\\Q")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector();
 			std::vector<RTLIL::State> arst_value = info.cell->parameters.at("\\ARST_VALUE").bits;
 			for (size_t i = 0; i < sig_d.size(); i++) {
 				info.bit_d = sig_d.at(i);
@@ -141,21 +141,21 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
 		}
 
 		if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") {
-			info.bit_clk = sigmap(info.cell->connections_.at("\\C")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit();
 			info.clk_polarity = info.cell->type == "$_DFF_P_";
-			info.bit_d = sigmap(info.cell->connections_.at("\\D")).to_single_sigbit();
+			info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit();
-			bit_info[sigmap(info.cell->connections_.at("\\Q")).to_single_sigbit()] = info;
+			bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info;
 			continue;
 		}
 
 		if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") {
-			info.bit_clk = sigmap(info.cell->connections_.at("\\C")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit();
-			info.bit_arst = sigmap(info.cell->connections_.at("\\R")).to_single_sigbit();
+			info.bit_arst = sigmap(info.cell->get("\\R")).to_single_sigbit();
 			info.clk_polarity = info.cell->type[6] == 'P';
 			info.arst_polarity = info.cell->type[7] == 'P';
 			info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0;
-			info.bit_d = sigmap(info.cell->connections_.at("\\D")).to_single_sigbit();
+			info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit();
-			bit_info[sigmap(info.cell->connections_.at("\\Q")).to_single_sigbit()] = info;
+			bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info;
 			continue;
 		}
 	}
@@ -514,11 +514,11 @@ struct ExposePass : public Pass {
 
 				for (auto &cell_name : info.cells) {
 					RTLIL::Cell *cell = module->cells.at(cell_name);
-					std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->connections_.at("\\Q")).to_sigbit_vector();
+					std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->get("\\Q")).to_sigbit_vector();
 					for (auto &bit : cell_q_bits)
 						if (wire_bits_set.count(bit))
 							bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++);
-					cell->connections_.at("\\Q") = cell_q_bits;
+					cell->set("\\Q", cell_q_bits);
 				}
 
 				RTLIL::Wire *wire_q = new RTLIL::Wire;
@@ -536,7 +536,7 @@ struct ExposePass : public Pass {
 					connect_q.second.append(RTLIL::SigBit(wire_q, i));
 					set_q_bits.insert(wire_bits_vec[i]);
 				}
-				module->connections_.push_back(connect_q);
+				module->connect(connect_q);
 
 				RTLIL::Wire *wire_d = new RTLIL::Wire;
 				wire_d->name = wire->name + sep + "d";
@@ -544,7 +544,7 @@ struct ExposePass : public Pass {
 				wire_d->port_output = true;
 				log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name));
 				add_new_wire(module, wire_d);
-				module->connections_.push_back(RTLIL::SigSig(wire_d, info.sig_d));
+				module->connect(RTLIL::SigSig(wire_d, info.sig_d));
 
 				RTLIL::Wire *wire_c = new RTLIL::Wire;
 				wire_c->name = wire->name + sep + "c";
@@ -552,14 +552,14 @@ struct ExposePass : public Pass {
 				log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name));
 				add_new_wire(module, wire_c);
 				if (info.clk_polarity) {
-					module->connections_.push_back(RTLIL::SigSig(wire_c, info.sig_clk));
+					module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
 				} else {
 					RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
 					c->parameters["\\A_SIGNED"] = 0;
 					c->parameters["\\A_WIDTH"] = 1;
 					c->parameters["\\Y_WIDTH"] = 1;
-					c->connections_["\\A"] = info.sig_clk;
+					c->set("\\A", info.sig_clk);
-					c->connections_["\\Y"] = wire_c;
+					c->set("\\Y", wire_c);
 				}
 
 				if (info.sig_arst != RTLIL::State::Sm)
@@ -570,14 +570,14 @@ struct ExposePass : public Pass {
 					log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name));
 					add_new_wire(module, wire_r);
 					if (info.arst_polarity) {
-						module->connections_.push_back(RTLIL::SigSig(wire_r, info.sig_arst));
+						module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
 					} else {
 						RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
 						c->parameters["\\A_SIGNED"] = 0;
 						c->parameters["\\A_WIDTH"] = 1;
 						c->parameters["\\Y_WIDTH"] = 1;
-						c->connections_["\\A"] = info.sig_arst;
+						c->set("\\A", info.sig_arst);
-						c->connections_["\\Y"] = wire_r;
+						c->set("\\Y", wire_r);
 					}
 
 					RTLIL::Wire *wire_v = new RTLIL::Wire;
@@ -586,7 +586,7 @@ struct ExposePass : public Pass {
 					wire_v->port_output = true;
 					log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name));
 					add_new_wire(module, wire_v);
-					module->connections_.push_back(RTLIL::SigSig(wire_v, info.arst_value));
+					module->connect(RTLIL::SigSig(wire_v, info.arst_value));
 				}
 			}
 
@@ -628,18 +628,18 @@ struct ExposePass : public Pass {
 							log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
 
 							RTLIL::SigSpec sig;
-							if (cell->connections_.count(p->name) != 0)
+							if (cell->connections().count(p->name) != 0)
-								sig = cell->connections_.at(p->name);
+								sig = cell->connections().at(p->name);
 							sig.extend(w->width);
 							if (w->port_input)
-								module->connections_.push_back(RTLIL::SigSig(sig, w));
+								module->connect(RTLIL::SigSig(sig, w));
 							else
-								module->connections_.push_back(RTLIL::SigSig(w, sig));
+								module->connect(RTLIL::SigSig(w, sig));
 						}
 					}
 					else
 					{
-						for (auto &it : cell->connections_)
+						for (auto &it : cell->connections())
 						{
 							RTLIL::Wire *w = new RTLIL::Wire;
 							w->name = cell->name + sep + RTLIL::unescape_id(it.first);
@@ -653,9 +653,9 @@ struct ExposePass : public Pass {
 							log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
 
 							if (w->port_input)
-								module->connections_.push_back(RTLIL::SigSig(it.second, w));
+								module->connect(RTLIL::SigSig(it.second, w));
 							else
-								module->connections_.push_back(RTLIL::SigSig(w, it.second));
+								module->connect(RTLIL::SigSig(w, it.second));
 						}
 					}
 

passes/sat/freduce.cc

@@ -610,7 +610,7 @@ struct FreduceWorker
 		for (auto &it : module->cells) {
 			if (ct.cell_known(it.second->type)) {
 				std::set<RTLIL::SigBit> inputs, outputs;
-				for (auto &port : it.second->connections_) {
+				for (auto &port : it.second->connections()) {
 					std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
 					if (ct.cell_output(it.second->type, port.first))
 						outputs.insert(bits.begin(), bits.end());
@@ -624,7 +624,7 @@ struct FreduceWorker
 				bits_full_total += outputs.size();
 			}
 			if (inv_mode && it.second->type == "$_INV_")
-				inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->connections_.at("\\A")), sigmap(it.second->connections_.at("\\Y"))));
+				inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->get("\\A")), sigmap(it.second->get("\\Y"))));
 		}
 
 		int bits_count = 0;
@@ -719,14 +719,14 @@ struct FreduceWorker
 						inv_sig = module->addWire(NEW_ID);
 
 						RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_");
-						inv_cell->connections_["\\A"] = grp[0].bit;
+						inv_cell->set("\\A", grp[0].bit);
-						inv_cell->connections_["\\Y"] = inv_sig;
+						inv_cell->set("\\Y", inv_sig);
 					}
 
-					module->connections_.push_back(RTLIL::SigSig(grp[i].bit, inv_sig));
+					module->connect(RTLIL::SigSig(grp[i].bit, inv_sig));
 				}
 				else
-					module->connections_.push_back(RTLIL::SigSig(grp[i].bit, grp[0].bit));
+					module->connect(RTLIL::SigSig(grp[i].bit, grp[0].bit));
 
 				rewired_sigbits++;
 			}

passes/sat/miter.cc

@@ -132,8 +132,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 			w2->width = w1->width;
 			miter_module->add(w2);
 
-			gold_cell->connections_[w1->name] = w2;
+			gold_cell->set(w1->name, w2);
-			gate_cell->connections_[w1->name] = w2;
+			gate_cell->set(w1->name, w2);
 		}
 
 		if (w1->port_output)
@@ -150,8 +150,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 			w2_gate->width = w1->width;
 			miter_module->add(w2_gate);
 
-			gold_cell->connections_[w1->name] = w2_gold;
+			gold_cell->set(w1->name, w2_gold);
-			gate_cell->connections_[w1->name] = w2_gate;
+			gate_cell->set(w1->name, w2_gate);
 
 			RTLIL::SigSpec this_condition;
 
@@ -165,9 +165,9 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 					eqx_cell->parameters["\\Y_WIDTH"] = 1;
 					eqx_cell->parameters["\\A_SIGNED"] = 0;
 					eqx_cell->parameters["\\B_SIGNED"] = 0;
-					eqx_cell->connections_["\\A"] = RTLIL::SigSpec(w2_gold, i);
+					eqx_cell->set("\\A", RTLIL::SigSpec(w2_gold, i));
-					eqx_cell->connections_["\\B"] = RTLIL::State::Sx;
+					eqx_cell->set("\\B", RTLIL::State::Sx);
-					eqx_cell->connections_["\\Y"] = gold_x.extract(i, 1);
+					eqx_cell->set("\\Y", gold_x.extract(i, 1));
 				}
 
 				RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width);
@@ -179,9 +179,9 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 				or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width;
 				or_gold_cell->parameters["\\A_SIGNED"] = 0;
 				or_gold_cell->parameters["\\B_SIGNED"] = 0;
-				or_gold_cell->connections_["\\A"] = w2_gold;
+				or_gold_cell->set("\\A", w2_gold);
-				or_gold_cell->connections_["\\B"] = gold_x;
+				or_gold_cell->set("\\B", gold_x);
-				or_gold_cell->connections_["\\Y"] = gold_masked;
+				or_gold_cell->set("\\Y", gold_masked);
 
 				RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or");
 				or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width;
@@ -189,9 +189,9 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 				or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width;
 				or_gate_cell->parameters["\\A_SIGNED"] = 0;
 				or_gate_cell->parameters["\\B_SIGNED"] = 0;
-				or_gate_cell->connections_["\\A"] = w2_gate;
+				or_gate_cell->set("\\A", w2_gate);
-				or_gate_cell->connections_["\\B"] = gold_x;
+				or_gate_cell->set("\\B", gold_x);
-				or_gate_cell->connections_["\\Y"] = gate_masked;
+				or_gate_cell->set("\\Y", gate_masked);
 
 				RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
 				eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
@@ -199,10 +199,10 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 				eq_cell->parameters["\\Y_WIDTH"] = 1;
 				eq_cell->parameters["\\A_SIGNED"] = 0;
 				eq_cell->parameters["\\B_SIGNED"] = 0;
-				eq_cell->connections_["\\A"] = gold_masked;
+				eq_cell->set("\\A", gold_masked);
-				eq_cell->connections_["\\B"] = gate_masked;
+				eq_cell->set("\\B", gate_masked);
-				eq_cell->connections_["\\Y"] = miter_module->addWire(NEW_ID);
+				eq_cell->set("\\Y", miter_module->addWire(NEW_ID));
-				this_condition = eq_cell->connections_["\\Y"];
+				this_condition = eq_cell->get("\\Y");
 			}
 			else
 			{
@@ -212,10 +212,10 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 				eq_cell->parameters["\\Y_WIDTH"] = 1;
 				eq_cell->parameters["\\A_SIGNED"] = 0;
 				eq_cell->parameters["\\B_SIGNED"] = 0;
-				eq_cell->connections_["\\A"] = w2_gold;
+				eq_cell->set("\\A", w2_gold);
-				eq_cell->connections_["\\B"] = w2_gate;
+				eq_cell->set("\\B", w2_gate);
-				eq_cell->connections_["\\Y"] = miter_module->addWire(NEW_ID);
+				eq_cell->set("\\Y", miter_module->addWire(NEW_ID));
-				this_condition = eq_cell->connections_["\\Y"];
+				this_condition = eq_cell->get("\\Y");
 			}
 
 			if (flag_make_outcmp)
@@ -224,7 +224,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 				w_cmp->name = "\\cmp_" + RTLIL::unescape_id(w1->name);
 				w_cmp->port_output = true;
 				miter_module->add(w_cmp);
-				miter_module->connections_.push_back(RTLIL::SigSig(w_cmp, this_condition));
+				miter_module->connect(RTLIL::SigSig(w_cmp, this_condition));
 			}
 
 			all_conditions.append(this_condition);
@@ -236,15 +236,15 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 		reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size();
 		reduce_cell->parameters["\\Y_WIDTH"] = 1;
 		reduce_cell->parameters["\\A_SIGNED"] = 0;
-		reduce_cell->connections_["\\A"] = all_conditions;
+		reduce_cell->set("\\A", all_conditions);
-		reduce_cell->connections_["\\Y"] = miter_module->addWire(NEW_ID);
+		reduce_cell->set("\\Y", miter_module->addWire(NEW_ID));
-		all_conditions = reduce_cell->connections_["\\Y"];
+		all_conditions = reduce_cell->get("\\Y");
 	}
 
 	if (flag_make_assert) {
 		RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert");
-		assert_cell->connections_["\\A"] = all_conditions;
+		assert_cell->set("\\A", all_conditions);
-		assert_cell->connections_["\\EN"] = RTLIL::SigSpec(1, 1);
+		assert_cell->set("\\EN", RTLIL::SigSpec(1, 1));
 	}
 
 	RTLIL::Wire *w_trigger = new RTLIL::Wire;
@@ -257,8 +257,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 	not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
 	not_cell->parameters["\\Y_WIDTH"] = w_trigger->width;
 	not_cell->parameters["\\A_SIGNED"] = 0;
-	not_cell->connections_["\\A"] = all_conditions;
+	not_cell->set("\\A", all_conditions);
-	not_cell->connections_["\\Y"] = w_trigger;
+	not_cell->set("\\Y", w_trigger);
 
 	miter_module->fixup_ports();
 

passes/sat/sat.cc

@@ -321,7 +321,7 @@ struct SatHelper
 			if (design->selected(module, c.second)) {
 				// log("Import cell: %s\n", RTLIL::id2cstr(c.first));
 				if (satgen.importCell(c.second, timestep)) {
-					for (auto &p : c.second->connections_)
+					for (auto &p : c.second->connections())
 						if (ct.cell_output(c.second->type, p.first))
 							show_drivers.insert(sigmap(p.second), c.second);
 					import_cell_counter++;
@@ -505,7 +505,7 @@ struct SatHelper
 					final_signals.add(sig);
 				} else {
 					for (auto &d : drivers)
-					for (auto &p : d->connections_) {
+					for (auto &p : d->connections()) {
 						if (d->type == "$dff" && p.first == "\\CLK")
 							continue;
 						if (d->type.substr(0, 6) == "$_DFF_" && p.first == "\\C")

passes/sat/share.cc

@@ -77,7 +77,7 @@ struct ShareWorker
 
 			for (auto &pbit : portbits) {
 				if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") {
-					std::set<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->connections_.at("\\S")).to_sigbit_set();
+					std::set<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->get("\\S")).to_sigbit_set();
 					terminal_bits.insert(bits.begin(), bits.end());
 					queue_bits.insert(bits.begin(), bits.end());
 					visited_cells.insert(pbit.cell);
@@ -256,9 +256,11 @@ struct ShareWorker
 			if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
 			{
 				RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
-				if (unsigned_cell->connections_.at("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
+				if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
 					unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
-					unsigned_cell->connections_.at("\\A").append_bit(RTLIL::State::S0);
+					RTLIL::SigSpec new_a = unsigned_cell->get("\\A");
+					new_a.append_bit(RTLIL::State::S0);
+					unsigned_cell->set("\\A", new_a);
 				}
 				unsigned_cell->parameters.at("\\A_SIGNED") = true;
 				unsigned_cell->check();
@@ -267,17 +269,17 @@ struct ShareWorker
 			bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool();
 			log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool());
 
-			RTLIL::SigSpec a1 = c1->connections_.at("\\A");
+			RTLIL::SigSpec a1 = c1->get("\\A");
-			RTLIL::SigSpec y1 = c1->connections_.at("\\Y");
+			RTLIL::SigSpec y1 = c1->get("\\Y");
 
-			RTLIL::SigSpec a2 = c2->connections_.at("\\A");
+			RTLIL::SigSpec a2 = c2->get("\\A");
-			RTLIL::SigSpec y2 = c2->connections_.at("\\Y");
+			RTLIL::SigSpec y2 = c2->get("\\Y");
 
 			int a_width = std::max(a1.size(), a2.size());
 			int y_width = std::max(y1.size(), y2.size());
 
-			if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y");
+			if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y");
-			if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y");
+			if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y");
 
 			RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
 			RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
@@ -286,14 +288,14 @@ struct ShareWorker
 			supercell->parameters["\\A_SIGNED"] = a_signed;
 			supercell->parameters["\\A_WIDTH"] = a_width;
 			supercell->parameters["\\Y_WIDTH"] = y_width;
-			supercell->connections_["\\A"] = a;
+			supercell->set("\\A", a);
-			supercell->connections_["\\Y"] = y;
+			supercell->set("\\Y", y);
 
 			RTLIL::SigSpec new_y1(y, 0, y1.size());
 			RTLIL::SigSpec new_y2(y, 0, y2.size());
 
-			module->connections_.push_back(RTLIL::SigSig(y1, new_y1));
+			module->connect(RTLIL::SigSig(y1, new_y1));
-			module->connections_.push_back(RTLIL::SigSig(y2, new_y2));
+			module->connect(RTLIL::SigSig(y2, new_y2));
 
 			return supercell;
 		}
@@ -312,7 +314,10 @@ struct ShareWorker
 
 				if (score_flipped < score_unflipped)
 				{
-					std::swap(c2->connections_.at("\\A"), c2->connections_.at("\\B"));
+					RTLIL::SigSpec tmp = c2->get("\\A");
+					c2->set("\\A", c2->get("\\B"));
+					c2->set("\\B", tmp);
+
 					std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH"));
 					std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED"));
 					modified_src_cells = true;
@@ -323,9 +328,11 @@ struct ShareWorker
 
 			{
 				RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
-				if (unsigned_cell->connections_.at("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
+				if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
 					unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
-					unsigned_cell->connections_.at("\\A").append_bit(RTLIL::State::S0);
+					RTLIL::SigSpec new_a = unsigned_cell->get("\\A");
+					new_a.append_bit(RTLIL::State::S0);
+					unsigned_cell->set("\\A", new_a);
 				}
 				unsigned_cell->parameters.at("\\A_SIGNED") = true;
 				modified_src_cells = true;
@@ -334,9 +341,11 @@ struct ShareWorker
 			if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool())
 			{
 				RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1;
-				if (unsigned_cell->connections_.at("\\B").to_sigbit_vector().back() != RTLIL::State::S0) {
+				if (unsigned_cell->get("\\B").to_sigbit_vector().back() != RTLIL::State::S0) {
 					unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1;
-					unsigned_cell->connections_.at("\\B").append_bit(RTLIL::State::S0);
+					RTLIL::SigSpec new_b = unsigned_cell->get("\\B");
+					new_b.append_bit(RTLIL::State::S0);
+					unsigned_cell->set("\\B", new_b);
 				}
 				unsigned_cell->parameters.at("\\B_SIGNED") = true;
 				modified_src_cells = true;
@@ -356,13 +365,13 @@ struct ShareWorker
 			if (c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr")
 				b_signed = false;
 
-			RTLIL::SigSpec a1 = c1->connections_.at("\\A");
+			RTLIL::SigSpec a1 = c1->get("\\A");
-			RTLIL::SigSpec b1 = c1->connections_.at("\\B");
+			RTLIL::SigSpec b1 = c1->get("\\B");
-			RTLIL::SigSpec y1 = c1->connections_.at("\\Y");
+			RTLIL::SigSpec y1 = c1->get("\\Y");
 
-			RTLIL::SigSpec a2 = c2->connections_.at("\\A");
+			RTLIL::SigSpec a2 = c2->get("\\A");
-			RTLIL::SigSpec b2 = c2->connections_.at("\\B");
+			RTLIL::SigSpec b2 = c2->get("\\B");
-			RTLIL::SigSpec y2 = c2->connections_.at("\\Y");
+			RTLIL::SigSpec y2 = c2->get("\\Y");
 
 			int a_width = std::max(a1.size(), a2.size());
 			int b_width = std::max(b1.size(), b2.size());
@@ -372,20 +381,20 @@ struct ShareWorker
 			{
 				a_width = std::max(y_width, a_width);
 
-				if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->connections_.at("\\Y");
+				if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->get("\\Y");
-				if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->connections_.at("\\Y");
+				if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->get("\\Y");
 
-				if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->connections_.at("\\Y");
+				if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->get("\\Y");
-				if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->connections_.at("\\Y");
+				if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->get("\\Y");
 			}
 			else
 			{
-				if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y");
+				if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y");
-				if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->connections_.at("\\Y");
+				if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y");
 			}
 
-			if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->connections_.at("\\Y");
+			if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->get("\\Y");
-			if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->connections_.at("\\Y");
+			if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->get("\\Y");
 
 			RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
 			RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act);
@@ -397,16 +406,16 @@ struct ShareWorker
 			supercell->parameters["\\A_WIDTH"] = a_width;
 			supercell->parameters["\\B_WIDTH"] = b_width;
 			supercell->parameters["\\Y_WIDTH"] = y_width;
-			supercell->connections_["\\A"] = a;
+			supercell->set("\\A", a);
-			supercell->connections_["\\B"] = b;
+			supercell->set("\\B", b);
-			supercell->connections_["\\Y"] = y;
+			supercell->set("\\Y", y);
 			supercell->check();
 
 			RTLIL::SigSpec new_y1(y, 0, y1.size());
 			RTLIL::SigSpec new_y2(y, 0, y2.size());
 
-			module->connections_.push_back(RTLIL::SigSig(y1, new_y1));
+			module->connect(RTLIL::SigSig(y1, new_y1));
-			module->connections_.push_back(RTLIL::SigSig(y2, new_y2));
+			module->connect(RTLIL::SigSig(y2, new_y2));
 
 			return supercell;
 		}
@@ -438,7 +447,7 @@ struct ShareWorker
 
 		for (auto &bit : pbits) {
 			if ((bit.cell->type == "$mux" || bit.cell->type == "$pmux") && bit.port == "\\S")
-				forbidden_controls_cache[cell].insert(bit.cell->connections_.at("\\S").extract(bit.offset, 1));
+				forbidden_controls_cache[cell].insert(bit.cell->get("\\S").extract(bit.offset, 1));
 			consumer_cells.insert(bit.cell);
 		}
 
@@ -532,9 +541,9 @@ struct ShareWorker
 			std::set<int> used_in_b_parts;
 
 			int width = c->parameters.at("\\WIDTH").as_int();
-			std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->connections_.at("\\A"));
+			std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->get("\\A"));
-			std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->connections_.at("\\B"));
+			std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->get("\\B"));
-			std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->connections_.at("\\S"));
+			std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->get("\\S"));
 
 			for (auto &bit : sig_a)
 				if (cell_out_bits.count(bit))
@@ -572,7 +581,7 @@ struct ShareWorker
 		if (activation_patterns_cache[cell].empty()) {
 			log("%sFound cell that is never activated: %s\n", indent, log_id(cell));
 			RTLIL::SigSpec cell_outputs = modwalker.cell_outputs[cell];
-			module->connections_.push_back(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size())));
+			module->connect(RTLIL::SigSig(cell_outputs, RTLIL::SigSpec(RTLIL::State::Sx, cell_outputs.size())));
 			cells_to_remove.insert(cell);
 		}
 

passes/techmap/dfflibmap.cc

@@ -398,7 +398,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 	{
 		auto cell_type = cell->type;
 		auto cell_name = cell->name;
-		auto cell_connections = cell->connections_;
+		auto cell_connections = cell->connections();
 		module->remove(cell);
 
 		cell_mapping &cm = cell_mappings[cell_type];
@@ -418,7 +418,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 			} else
 			if (port.second != 0)
 				log_abort();
-			new_cell->connections_["\\" + port.first] = sig;
+			new_cell->set("\\" + port.first, sig);
 		}
 
 		stats[stringf("  mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++;

passes/techmap/extract.cc

@@ -125,10 +125,10 @@ namespace
 				RTLIL::Wire *lastHaystackWire = NULL;
 				std::map<RTLIL::IdString, RTLIL::Const> emptyAttr;
 
-				for (auto &conn : needleCell->connections_)
+				for (auto &conn : needleCell->connections())
 				{
 					RTLIL::SigSpec needleSig = conn.second;
-					RTLIL::SigSpec haystackSig = haystackCell->connections_.at(portMapping.at(conn.first));
+					RTLIL::SigSpec haystackSig = haystackCell->connections().at(portMapping.at(conn.first));
 
 					for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
 						RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
@@ -186,7 +186,7 @@ namespace
 			{
 				RTLIL::Cell *cell = cell_it.second;
 				if (!sel || sel->selected(mod, cell))
-					for (auto &conn : cell->connections_) {
+					for (auto &conn : cell->connections()) {
 						RTLIL::SigSpec conn_sig = conn.second;
 						sigmap.apply(conn_sig);
 						for (auto &bit : conn_sig)
@@ -207,7 +207,7 @@ namespace
 				type = type.substr(1);
 			graph.createNode(cell->name, type, (void*)cell);
 
-			for (auto &conn : cell->connections_)
+			for (auto &conn : cell->connections())
 			{
 				graph.createPort(cell->name, conn.first, conn.second.size());
 
@@ -257,7 +257,7 @@ namespace
 		{
 			RTLIL::Cell *cell = cell_it.second;
 			if (sel && !sel->selected(mod, cell))
-				for (auto &conn : cell->connections_)
+				for (auto &conn : cell->connections())
 				{
 					RTLIL::SigSpec conn_sig = conn.second;
 					sigmap.apply(conn_sig);
@@ -305,7 +305,7 @@ namespace
 			if (wire->port_id > 0) {
 				for (int i = 0; i < wire->width; i++)
 					sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<std::string, int>(wire->name, i));
-				cell->connections_[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width);
+				cell->set(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
 			}
 		}
 
@@ -319,13 +319,15 @@ namespace
 			if (needle_cell == NULL)
 				continue;
 
-			for (auto &conn : needle_cell->connections_) {
+			for (auto &conn : needle_cell->connections()) {
 				RTLIL::SigSpec sig = sigmap(conn.second);
 				if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
 					for (int i = 0; i < sig.size(); i++)
 					for (auto &port : sig2port.find(sig[i])) {
-						RTLIL::SigSpec bitsig = haystack_cell->connections_.at(mapping.portMapping[conn.first]).extract(i, 1);
+						RTLIL::SigSpec bitsig = haystack_cell->connections().at(mapping.portMapping[conn.first]).extract(i, 1);
-						cell->connections_.at(port.first).replace(port.second, bitsig);
+						RTLIL::SigSpec new_sig = cell->get(port.first);
+						new_sig.replace(port.second, bitsig);
+						cell->set(port.first, new_sig);
 					}
 				}
 			}
@@ -714,7 +716,7 @@ struct ExtractPass : public Pass {
 					cells.insert((RTLIL::Cell*)node.userData);
 
 				for (auto cell : cells)
-				for (auto &conn : cell->connections_) {
+				for (auto &conn : cell->connections()) {
 					RTLIL::SigSpec sig = sigmap(conn.second);
 					for (auto &chunk : sig.chunks())
 						if (chunk.wire != NULL)
@@ -739,12 +741,12 @@ struct ExtractPass : public Pass {
 				for (auto cell : cells) {
 					RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
 					newCell->parameters = cell->parameters;
-					for (auto &conn : cell->connections_) {
+					for (auto &conn : cell->connections()) {
 						std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second);
 						for (auto &chunk : chunks)
 							if (chunk.wire != NULL)
 								chunk.wire = newMod->wires.at(chunk.wire->name);
-						newCell->connections_[conn.first] = chunks;
+						newCell->set(conn.first, chunks);
 					}
 				}
 			}

passes/techmap/hilomap.cc

@@ -35,7 +35,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 			if (!singleton_mode || last_hi == RTLIL::State::Sm) {
 				last_hi = module->addWire(NEW_ID);
 				RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
-				cell->connections_[RTLIL::escape_id(hicell_portname)] = last_hi;
+				cell->set(RTLIL::escape_id(hicell_portname), last_hi);
 			}
 			bit = last_hi;
 		}
@@ -43,7 +43,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 			if (!singleton_mode || last_lo == RTLIL::State::Sm) {
 				last_lo = module->addWire(NEW_ID);
 				RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
-				cell->connections_[RTLIL::escape_id(locell_portname)] = last_lo;
+				cell->set(RTLIL::escape_id(locell_portname), last_lo);
 			}
 			bit = last_lo;
 		}

passes/techmap/iopadmap.cc

@@ -177,9 +177,9 @@ struct IopadmapPass : public Pass {
 					for (int i = 0; i < wire->width; i++)
 					{
 						RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
-						cell->connections_[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
+						cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
 						if (!portname2.empty())
-							cell->connections_[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
+							cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i));
 						if (!widthparam.empty())
 							cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
 						if (!nameparam.empty())
@@ -190,9 +190,9 @@ struct IopadmapPass : public Pass {
 				else
 				{
 					RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
-					cell->connections_[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire);
+					cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire));
 					if (!portname2.empty())
-						cell->connections_[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire);
+						cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire));
 					if (!widthparam.empty())
 						cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
 					if (!nameparam.empty())

passes/techmap/simplemap.cc

@@ -29,43 +29,43 @@ extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*,
 
 static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
 	for (int i = 0; i < SIZE(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
-		gate->connections_["\\A"] = sig_a[i];
+		gate->set("\\A", sig_a[i]);
-		gate->connections_["\\Y"] = sig_y[i];
+		gate->set("\\Y", sig_y[i]);
 	}
 }
 
 static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
-	module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a));
+	module->connect(RTLIL::SigSig(sig_y, sig_a));
 }
 
 static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
-	module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a));
+	module->connect(RTLIL::SigSig(sig_y, sig_a));
 }
 
 static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
-	RTLIL::SigSpec sig_b = cell->connections_.at("\\B");
+	RTLIL::SigSpec sig_b = cell->get("\\B");
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 	sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
@@ -76,8 +76,8 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 
 		for (int i = 0; i < SIZE(sig_y); i++) {
 			RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
-			gate->connections_["\\A"] = sig_t[i];
+			gate->set("\\A", sig_t[i]);
-			gate->connections_["\\Y"] = sig_y[i];
+			gate->set("\\Y", sig_y[i]);
 		}
 
 		sig_y = sig_t;
@@ -92,31 +92,31 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < SIZE(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->connections_["\\A"] = sig_a[i];
+		gate->set("\\A", sig_a[i]);
-		gate->connections_["\\B"] = sig_b[i];
+		gate->set("\\B", sig_b[i]);
-		gate->connections_["\\Y"] = sig_y[i];
+		gate->set("\\Y", sig_y[i]);
 	}
 }
 
 static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	if (sig_y.size() == 0)
 		return;
 	
 	if (sig_a.size() == 0) {
-		if (cell->type == "$reduce_and")  module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
+		if (cell->type == "$reduce_and")  module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
-		if (cell->type == "$reduce_or")   module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+		if (cell->type == "$reduce_or")   module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
-		if (cell->type == "$reduce_xor")  module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+		if (cell->type == "$reduce_xor")  module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
-		if (cell->type == "$reduce_xnor") module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
+		if (cell->type == "$reduce_xnor") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
-		if (cell->type == "$reduce_bool") module->connections_.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
+		if (cell->type == "$reduce_bool") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
 		return;
 	}
 
 	if (sig_y.size() > 1) {
-		module->connections_.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
+		module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
 		sig_y = sig_y.extract(0, 1);
 	}
 
@@ -128,7 +128,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 	if (cell->type == "$reduce_bool") gate_type = "$_OR_";
 	log_assert(!gate_type.empty());
 
-	RTLIL::SigSpec *last_output = NULL;
+	RTLIL::Cell *last_output_cell = NULL;
 
 	while (sig_a.size() > 1)
 	{
@@ -142,10 +142,10 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 			}
 
 			RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-			gate->connections_["\\A"] = sig_a[i];
+			gate->set("\\A", sig_a[i]);
-			gate->connections_["\\B"] = sig_a[i+1];
+			gate->set("\\B", sig_a[i+1]);
-			gate->connections_["\\Y"] = sig_t[i/2];
+			gate->set("\\Y", sig_t[i/2]);
-			last_output = &gate->connections_["\\Y"];
+			last_output_cell = gate;
 		}
 
 		sig_a = sig_t;
@@ -154,16 +154,16 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 	if (cell->type == "$reduce_xnor") {
 		RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
 		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
-		gate->connections_["\\A"] = sig_a;
+		gate->set("\\A", sig_a);
-		gate->connections_["\\Y"] = sig_t;
+		gate->set("\\Y", sig_t);
-		last_output = &gate->connections_["\\Y"];
+		last_output_cell = gate;
 		sig_a = sig_t;
 	}
 
-	if (last_output == NULL) {
+	if (last_output_cell == NULL) {
-		module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a));
+		module->connect(RTLIL::SigSig(sig_y, sig_a));
 	} else {
-		*last_output = sig_y;
+		last_output_cell->set("\\Y", sig_y);
 	}
 }
 
@@ -181,9 +181,9 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
 			}
 
 			RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_");
-			gate->connections_["\\A"] = sig[i];
+			gate->set("\\A", sig[i]);
-			gate->connections_["\\B"] = sig[i+1];
+			gate->set("\\B", sig[i+1]);
-			gate->connections_["\\Y"] = sig_t[i/2];
+			gate->set("\\Y", sig_t[i/2]);
 		}
 
 		sig = sig_t;
@@ -195,39 +195,39 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
 
 static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
 	logic_reduce(module, sig_a);
 
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	if (sig_y.size() == 0)
 		return;
 	
 	if (sig_y.size() > 1) {
-		module->connections_.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
+		module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
 		sig_y = sig_y.extract(0, 1);
 	}
 
 	RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
-	gate->connections_["\\A"] = sig_a;
+	gate->set("\\A", sig_a);
-	gate->connections_["\\Y"] = sig_y;
+	gate->set("\\Y", sig_y);
 }
 
 static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
 	logic_reduce(module, sig_a);
 
-	RTLIL::SigSpec sig_b = cell->connections_.at("\\B");
+	RTLIL::SigSpec sig_b = cell->get("\\B");
 	logic_reduce(module, sig_b);
 
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	if (sig_y.size() == 0)
 		return;
 	
 	if (sig_y.size() > 1) {
-		module->connections_.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
+		module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
 		sig_y = sig_y.extract(0, 1);
 	}
 
@@ -237,40 +237,40 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
 	log_assert(!gate_type.empty());
 
 	RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-	gate->connections_["\\A"] = sig_a;
+	gate->set("\\A", sig_a);
-	gate->connections_["\\B"] = sig_b;
+	gate->set("\\B", sig_b);
-	gate->connections_["\\Y"] = sig_y;
+	gate->set("\\Y", sig_y);
 }
 
 static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
-	RTLIL::SigSpec sig_b = cell->connections_.at("\\B");
+	RTLIL::SigSpec sig_b = cell->get("\\B");
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
 
 	for (int i = 0; i < SIZE(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
-		gate->connections_["\\A"] = sig_a[i];
+		gate->set("\\A", sig_a[i]);
-		gate->connections_["\\B"] = sig_b[i];
+		gate->set("\\B", sig_b[i]);
-		gate->connections_["\\S"] = cell->connections_.at("\\S");
+		gate->set("\\S", cell->get("\\S"));
-		gate->connections_["\\Y"] = sig_y[i];
+		gate->set("\\Y", sig_y[i]);
 	}
 }
 
 static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
 {
 	int offset = cell->parameters.at("\\OFFSET").as_int();
-	RTLIL::SigSpec sig_a = cell->connections_.at("\\A");
+	RTLIL::SigSpec sig_a = cell->get("\\A");
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
-	module->connections_.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
+	module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
 }
 
 static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_ab = cell->connections_.at("\\A");
+	RTLIL::SigSpec sig_ab = cell->get("\\A");
-	sig_ab.append(cell->connections_.at("\\B"));
+	sig_ab.append(cell->get("\\B"));
-	RTLIL::SigSpec sig_y = cell->connections_.at("\\Y");
+	RTLIL::SigSpec sig_y = cell->get("\\Y");
-	module->connections_.push_back(RTLIL::SigSig(sig_y, sig_ab));
+	module->connect(RTLIL::SigSig(sig_y, sig_ab));
 }
 
 static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
@@ -279,17 +279,17 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
 	char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
 	char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
 
-	RTLIL::SigSpec sig_s = cell->connections_.at("\\SET");
+	RTLIL::SigSpec sig_s = cell->get("\\SET");
-	RTLIL::SigSpec sig_r = cell->connections_.at("\\CLR");
+	RTLIL::SigSpec sig_r = cell->get("\\CLR");
-	RTLIL::SigSpec sig_q = cell->connections_.at("\\Q");
+	RTLIL::SigSpec sig_q = cell->get("\\Q");
 
 	std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->connections_["\\S"] = sig_s[i];
+		gate->set("\\S", sig_s[i]);
-		gate->connections_["\\R"] = sig_r[i];
+		gate->set("\\R", sig_r[i]);
-		gate->connections_["\\Q"] = sig_q[i];
+		gate->set("\\Q", sig_q[i]);
 	}
 }
 
@@ -298,17 +298,17 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
 	int width = cell->parameters.at("\\WIDTH").as_int();
 	char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
 
-	RTLIL::SigSpec sig_clk = cell->connections_.at("\\CLK");
+	RTLIL::SigSpec sig_clk = cell->get("\\CLK");
-	RTLIL::SigSpec sig_d = cell->connections_.at("\\D");
+	RTLIL::SigSpec sig_d = cell->get("\\D");
-	RTLIL::SigSpec sig_q = cell->connections_.at("\\Q");
+	RTLIL::SigSpec sig_q = cell->get("\\Q");
 
 	std::string gate_type = stringf("$_DFF_%c_", clk_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->connections_["\\C"] = sig_clk;
+		gate->set("\\C", sig_clk);
-		gate->connections_["\\D"] = sig_d[i];
+		gate->set("\\D", sig_d[i]);
-		gate->connections_["\\Q"] = sig_q[i];
+		gate->set("\\Q", sig_q[i]);
 	}
 }
 
@@ -319,21 +319,21 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
 	char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
 	char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
 
-	RTLIL::SigSpec sig_clk = cell->connections_.at("\\CLK");
+	RTLIL::SigSpec sig_clk = cell->get("\\CLK");
-	RTLIL::SigSpec sig_s = cell->connections_.at("\\SET");
+	RTLIL::SigSpec sig_s = cell->get("\\SET");
-	RTLIL::SigSpec sig_r = cell->connections_.at("\\CLR");
+	RTLIL::SigSpec sig_r = cell->get("\\CLR");
-	RTLIL::SigSpec sig_d = cell->connections_.at("\\D");
+	RTLIL::SigSpec sig_d = cell->get("\\D");
-	RTLIL::SigSpec sig_q = cell->connections_.at("\\Q");
+	RTLIL::SigSpec sig_q = cell->get("\\Q");
 
 	std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->connections_["\\C"] = sig_clk;
+		gate->set("\\C", sig_clk);
-		gate->connections_["\\S"] = sig_s[i];
+		gate->set("\\S", sig_s[i]);
-		gate->connections_["\\R"] = sig_r[i];
+		gate->set("\\R", sig_r[i]);
-		gate->connections_["\\D"] = sig_d[i];
+		gate->set("\\D", sig_d[i]);
-		gate->connections_["\\Q"] = sig_q[i];
+		gate->set("\\Q", sig_q[i]);
 	}
 }
 
@@ -347,20 +347,20 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
 	while (int(rst_val.size()) < width)
 		rst_val.push_back(RTLIL::State::S0);
 
-	RTLIL::SigSpec sig_clk = cell->connections_.at("\\CLK");
+	RTLIL::SigSpec sig_clk = cell->get("\\CLK");
-	RTLIL::SigSpec sig_rst = cell->connections_.at("\\ARST");
+	RTLIL::SigSpec sig_rst = cell->get("\\ARST");
-	RTLIL::SigSpec sig_d = cell->connections_.at("\\D");
+	RTLIL::SigSpec sig_d = cell->get("\\D");
-	RTLIL::SigSpec sig_q = cell->connections_.at("\\Q");
+	RTLIL::SigSpec sig_q = cell->get("\\Q");
 
 	std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
 	std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
-		gate->connections_["\\C"] = sig_clk;
+		gate->set("\\C", sig_clk);
-		gate->connections_["\\R"] = sig_rst;
+		gate->set("\\R", sig_rst);
-		gate->connections_["\\D"] = sig_d[i];
+		gate->set("\\D", sig_d[i]);
-		gate->connections_["\\Q"] = sig_q[i];
+		gate->set("\\Q", sig_q[i]);
 	}
 }
 
@@ -369,17 +369,17 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
 	int width = cell->parameters.at("\\WIDTH").as_int();
 	char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
 
-	RTLIL::SigSpec sig_en = cell->connections_.at("\\EN");
+	RTLIL::SigSpec sig_en = cell->get("\\EN");
-	RTLIL::SigSpec sig_d = cell->connections_.at("\\D");
+	RTLIL::SigSpec sig_d = cell->get("\\D");
-	RTLIL::SigSpec sig_q = cell->connections_.at("\\Q");
+	RTLIL::SigSpec sig_q = cell->get("\\Q");
 
 	std::string gate_type = stringf("$_DLATCH_%c_", en_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->connections_["\\E"] = sig_en;
+		gate->set("\\E", sig_en);
-		gate->connections_["\\D"] = sig_d[i];
+		gate->set("\\D", sig_d[i]);
-		gate->connections_["\\Q"] = sig_q[i];
+		gate->set("\\Q", sig_q[i]);
 	}
 }
 

passes/techmap/techmap.cc

@@ -141,7 +141,7 @@ struct TechmapWorker
 
 		SigMap port_signal_map;
 
-		for (auto &it : cell->connections_) {
+		for (auto &it : cell->connections()) {
 			RTLIL::IdString portname = it.first;
 			if (positional_ports.count(portname) > 0)
 				portname = positional_ports.at(portname);
@@ -169,7 +169,7 @@ struct TechmapWorker
 			if (flatten_mode) {
 				// more conservative approach:
 				// connect internal and external wires
-				module->connections_.push_back(c);
+				module->connect(c);
 			} else {
 				// approach that yields nicer outputs:
 				// replace internal wires that are connected to external wires
@@ -201,13 +201,13 @@ struct TechmapWorker
 			}
 		}
 
-		for (auto &it : tpl->connections_) {
+		for (auto &it : tpl->connections()) {
 			RTLIL::SigSig c = it;
 			apply_prefix(cell->name, c.first, module);
 			apply_prefix(cell->name, c.second, module);
 			port_signal_map.apply(c.first);
 			port_signal_map.apply(c.second);
-			module->connections_.push_back(c);
+			module->connect(c);
 		}
 
 		module->remove(cell);
@@ -262,7 +262,7 @@ struct TechmapWorker
 						break;
 					}
 
-					for (auto conn : cell->connections_) {
+					for (auto conn : cell->connections()) {
 						if (conn.first.substr(0, 1) == "$")
 							continue;
 						if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0)
@@ -280,7 +280,7 @@ struct TechmapWorker
 					if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
 						parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);
 
-					for (auto conn : cell->connections_) {
+					for (auto conn : cell->connections()) {
 						if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
 							std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
 							for (auto &bit : v)
@@ -303,7 +303,7 @@ struct TechmapWorker
 					unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
 					unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
 
-					for (auto conn : cell->connections_)
+					for (auto conn : cell->connections())
 						if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
 							for (auto &bit : sigmap(conn.second).to_sigbit_vector())
 								if (unique_bit_id.count(bit) == 0)
@@ -317,7 +317,7 @@ struct TechmapWorker
 					if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_"))
 						parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits;
 
-					for (auto conn : cell->connections_)
+					for (auto conn : cell->connections())
 						if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
 							RTLIL::Const value;
 							for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {