riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

A few modifications after pull request comments 

- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
This commit is contained in:
Ruben Undheim 2016-06-18 14:13:36 +02:00
parent 178ff3e7f6
commit a8200a773f
3 changed files with 4 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
frontends/ast/ast.cc
View File

@ -997,7 +997,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
for (auto n : global_decls) for (auto n : global_decls)
(*it)->children.push_back(n->clone()); (*it)->children.push_back(n->clone());
for (auto n : design->packages){ for (auto n : design->verilog_packages){
for (auto o : n->children) { for (auto o : n->children) {
AstNode *cloned_node = o->clone(); AstNode *cloned_node = o->clone();
cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1); cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1);
@ -1023,7 +1023,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
design->add(process_module(*it, defer)); design->add(process_module(*it, defer));
} }
else if ((*it)->type == AST_PACKAGE){ else if ((*it)->type == AST_PACKAGE){
design->packages.push_back((*it)->clone()); design->verilog_packages.push_back((*it)->clone());
} }
else else
global_decls.push_back(*it); global_decls.push_back(*it);

2
kernel/rtlil.cc
View File

@ -304,7 +304,7 @@ RTLIL::Design::~Design()
{ {
for (auto it = modules_.begin(); it != modules_.end(); ++it) for (auto it = modules_.begin(); it != modules_.end(); ++it)
delete it->second; delete it->second;
for (auto n : packages) for (auto n : verilog_packages)
delete n; delete n;
} }

3
kernel/rtlil.h
View File

@ -18,7 +18,6 @@
*/ */
#include "kernel/yosys.h" #include "kernel/yosys.h"
#include "frontends/ast/ast.h"
#ifndef RTLIL_H #ifndef RTLIL_H
#define RTLIL_H #define RTLIL_H
@ -793,7 +792,7 @@ struct RTLIL::Design
int refcount_modules_; int refcount_modules_;
dict<RTLIL::IdString, RTLIL::Module*> modules_; dict<RTLIL::IdString, RTLIL::Module*> modules_;
std::vector<AST::AstNode*> packages; std::vector<AST::AstNode*> verilog_packages;
std::vector<RTLIL::Selection> selection_stack; std::vector<RTLIL::Selection> selection_stack;
dict<RTLIL::IdString, RTLIL::Selection> selection_vars; dict<RTLIL::IdString, RTLIL::Selection> selection_vars;