mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #808 from eddiehung/read_aiger
Add new read_aiger frontend
This commit is contained in:
Eddie Hung
GitHub
commit
a7ac8393d4
1
Makefile
1
Makefile
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@ -585,6 +585,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
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+cd tests/sat && bash run-test.sh
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+cd tests/svinterfaces && bash run-test.sh $(SEEDOPT)
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+cd tests/opt && bash run-test.sh
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+cd tests/aiger && bash run-test.sh
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@echo ""
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@echo " Passed \"make test\"."
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@echo ""
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@ -0,0 +1,3 @@
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OBJS += frontends/aiger/aigerparse.o
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@ -0,0 +1,414 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// [[CITE]] The AIGER And-Inverter Graph (AIG) Format Version 20071012
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// Armin Biere. The AIGER And-Inverter Graph (AIG) Format Version 20071012. Technical Report 07/1, October 2011, FMV Reports Series, Institute for Formal Models and Verification, Johannes Kepler University, Altenbergerstr. 69, 4040 Linz, Austria.
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// http://fmv.jku.at/papers/Biere-FMV-TR-07-1.pdf
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#ifndef _WIN32
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#include <libgen.h>
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#endif
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#include <array>
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "aigerparse.h"
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YOSYS_NAMESPACE_BEGIN
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#define log_debug log
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AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name)
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: design(design), f(f), clk_name(clk_name)
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{
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module = new RTLIL::Module;
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module->name = module_name;
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if (design->module(module->name))
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log_error("Duplicate definition of module %s!\n", log_id(module->name));
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}
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void AigerReader::parse_aiger()
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{
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std::string header;
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f >> header;
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if (header != "aag" && header != "aig")
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log_error("Unsupported AIGER file!\n");
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// Parse rest of header
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if (!(f >> M >> I >> L >> O >> A))
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log_error("Invalid AIGER header\n");
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// Optional values
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B = C = J = F = 0;
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for (auto &i : std::array<std::reference_wrapper<unsigned>,4>{B, C, J, F}) {
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if (f.peek() != ' ') break;
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if (!(f >> i))
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log_error("Invalid AIGER header\n");
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}
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std::string line;
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std::getline(f, line); // Ignore up to start of next line, as standard
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// says anything that follows could be used for
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// optional sections
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log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F);
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line_count = 1;
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if (header == "aag")
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parse_aiger_ascii();
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else if (header == "aig")
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parse_aiger_binary();
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else
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log_abort();
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// Parse footer (symbol table, comments, etc.)
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unsigned l1;
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std::string s;
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for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
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if (c == 'i' || c == 'l' || c == 'o') {
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f.ignore(1);
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if (!(f >> l1 >> s))
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log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
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if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
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log_error("Line %u has invalid symbol position!\n", line_count);
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RTLIL::Wire* wire;
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if (c == 'i') wire = inputs[l1];
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else if (c == 'l') wire = latches[l1];
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else if (c == 'o') wire = outputs[l1];
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else log_abort();
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module->rename(wire, stringf("\\%s", s.c_str()));
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}
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else if (c == 'b' || c == 'j' || c == 'f') {
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// TODO
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}
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else if (c == 'c') {
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f.ignore(1);
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if (f.peek() == '\n')
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break;
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// Else constraint (TODO)
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}
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else
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log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
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std::getline(f, line); // Ignore up to start of next line
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}
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module->fixup_ports();
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design->add(module);
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}
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static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal)
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{
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const unsigned variable = literal >> 1;
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const bool invert = literal & 1;
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RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix?
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RTLIL::Wire *wire = module->wire(wire_name);
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if (wire) return wire;
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log_debug("Creating %s\n", wire_name.c_str());
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wire = module->addWire(wire_name);
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if (!invert) return wire;
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RTLIL::IdString wire_inv_name(stringf("\\n%d", variable));
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RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
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if (wire_inv) {
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if (module->cell(wire_inv_name)) return wire;
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}
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else {
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log_debug("Creating %s\n", wire_inv_name.c_str());
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wire_inv = module->addWire(wire_inv_name);
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}
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log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
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module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix?
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return wire;
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}
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void AigerReader::parse_aiger_ascii()
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{
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std::string line;
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std::stringstream ss;
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unsigned l1, l2, l3;
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// Parse inputs
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for (unsigned i = 0; i < I; ++i, ++line_count) {
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an input!\n", line_count);
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log_debug("%d is an input\n", l1);
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log_assert(!(l1 & 1)); // TODO: Inputs can't be inverted?
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RTLIL::Wire *wire = createWireIfNotExists(module, l1);
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wire->port_input = true;
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inputs.push_back(wire);
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}
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// Parse latches
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RTLIL::Wire *clk_wire = nullptr;
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if (L > 0) {
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clk_wire = module->wire(clk_name);
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log_assert(!clk_wire);
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log_debug("Creating %s\n", clk_name.c_str());
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clk_wire = module->addWire(clk_name);
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clk_wire->port_input = true;
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}
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for (unsigned i = 0; i < L; ++i, ++line_count) {
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if (!(f >> l1 >> l2))
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log_error("Line %u cannot be interpreted as a latch!\n", line_count);
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log_debug("%d %d is a latch\n", l1, l2);
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log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted?
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RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
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module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire);
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// Reset logic is optional in AIGER 1.9
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if (f.peek() == ' ') {
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if (!(f >> l3))
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log_error("Line %u cannot be interpreted as a latch!\n", line_count);
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if (l3 == 0 || l3 == 1)
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q_wire->attributes["\\init"] = RTLIL::Const(l3);
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else if (l3 == l1) {
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//q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
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}
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else
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log_error("Line %u has invalid reset literal for latch!\n", line_count);
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}
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else {
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// AIGER latches are assumed to be initialized to zero
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q_wire->attributes["\\init"] = RTLIL::Const(0);
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}
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latches.push_back(q_wire);
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}
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// Parse outputs
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for (unsigned i = 0; i < O; ++i, ++line_count) {
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an output!\n", line_count);
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log_debug("%d is an output\n", l1);
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RTLIL::Wire *wire = createWireIfNotExists(module, l1);
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wire->port_output = true;
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outputs.push_back(wire);
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}
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std::getline(f, line); // Ignore up to start of next line
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// TODO: Parse bad state properties
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for (unsigned i = 0; i < B; ++i, ++line_count)
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std::getline(f, line); // Ignore up to start of next line
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// TODO: Parse invariant constraints
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for (unsigned i = 0; i < C; ++i, ++line_count)
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std::getline(f, line); // Ignore up to start of next line
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// TODO: Parse justice properties
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for (unsigned i = 0; i < J; ++i, ++line_count)
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std::getline(f, line); // Ignore up to start of next line
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// TODO: Parse fairness constraints
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for (unsigned i = 0; i < F; ++i, ++line_count)
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std::getline(f, line); // Ignore up to start of next line
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// Parse AND
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for (unsigned i = 0; i < A; ++i) {
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if (!(f >> l1 >> l2 >> l3))
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log_error("Line %u cannot be interpreted as an AND!\n", line_count);
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log_debug("%d %d %d is an AND\n", l1, l2, l3);
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log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
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RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
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RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
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module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
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}
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std::getline(f, line); // Ignore up to start of next line
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}
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static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
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{
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unsigned x = 0, i = 0;
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unsigned char ch;
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while ((ch = f.get()) & 0x80)
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x |= (ch & 0x7f) << (7 * i++);
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return ref - (x | (ch << (7 * i)));
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}
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void AigerReader::parse_aiger_binary()
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{
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unsigned l1, l2, l3;
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std::string line;
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// Parse inputs
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for (unsigned i = 1; i <= I; ++i) {
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RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
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wire->port_input = true;
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inputs.push_back(wire);
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}
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// Parse latches
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RTLIL::Wire *clk_wire = nullptr;
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if (L > 0) {
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clk_wire = module->wire(clk_name);
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log_assert(!clk_wire);
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log_debug("Creating %s\n", clk_name.c_str());
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clk_wire = module->addWire(clk_name);
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clk_wire->port_input = true;
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}
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l1 = (I+1) * 2;
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for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) {
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if (!(f >> l2))
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log_error("Line %u cannot be interpreted as a latch!\n", line_count);
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log_debug("%d %d is a latch\n", l1, l2);
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RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
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module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
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// Reset logic is optional in AIGER 1.9
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if (f.peek() == ' ') {
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if (!(f >> l3))
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log_error("Line %u cannot be interpreted as a latch!\n", line_count);
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if (l3 == 0 || l3 == 1)
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q_wire->attributes["\\init"] = RTLIL::Const(l3);
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else if (l3 == l1) {
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//q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
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}
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else
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log_error("Line %u has invalid reset literal for latch!\n", line_count);
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}
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else {
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// AIGER latches are assumed to be initialized to zero
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q_wire->attributes["\\init"] = RTLIL::Const(0);
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}
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latches.push_back(q_wire);
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}
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// Parse outputs
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for (unsigned i = 0; i < O; ++i, ++line_count) {
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an output!\n", line_count);
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log_debug("%d is an output\n", l1);
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RTLIL::Wire *wire = createWireIfNotExists(module, l1);
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wire->port_output = true;
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outputs.push_back(wire);
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}
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std::getline(f, line); // Ignore up to start of next line
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// TODO: Parse bad state properties
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for (unsigned i = 0; i < B; ++i, ++line_count)
|
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std::getline(f, line); // Ignore up to start of next line
|
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|
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// TODO: Parse invariant constraints
|
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for (unsigned i = 0; i < C; ++i, ++line_count)
|
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std::getline(f, line); // Ignore up to start of next line
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|
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// TODO: Parse justice properties
|
||||
for (unsigned i = 0; i < J; ++i, ++line_count)
|
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std::getline(f, line); // Ignore up to start of next line
|
||||
|
||||
// TODO: Parse fairness constraints
|
||||
for (unsigned i = 0; i < F; ++i, ++line_count)
|
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std::getline(f, line); // Ignore up to start of next line
|
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// Parse AND
|
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l1 = (I+L+1) << 1;
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for (unsigned i = 0; i < A; ++i, ++line_count, l1 += 2) {
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l2 = parse_next_delta_literal(f, l1);
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l3 = parse_next_delta_literal(f, l2);
|
||||
|
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log_debug("%d %d %d is an AND\n", l1, l2, l3);
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log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
|
||||
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
|
||||
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
|
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RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
|
||||
|
||||
RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
|
||||
and_cell->setPort("\\A", i1_wire);
|
||||
and_cell->setPort("\\B", i2_wire);
|
||||
and_cell->setPort("\\Y", o_wire);
|
||||
}
|
||||
}
|
||||
|
||||
struct AigerFrontend : public Frontend {
|
||||
AigerFrontend() : Frontend("aiger", "read AIGER file") { }
|
||||
void help() YS_OVERRIDE
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" read_aiger [options] [filename]\n");
|
||||
log("\n");
|
||||
log("Load module from an AIGER file into the current design.\n");
|
||||
log("\n");
|
||||
log(" -module_name <module_name>\n");
|
||||
log(" Name of module to be created (default: <filename>)"
|
||||
#ifdef _WIN32
|
||||
"top" // FIXME
|
||||
#else
|
||||
"<filename>"
|
||||
#endif
|
||||
")\n");
|
||||
log("\n");
|
||||
log(" -clk_name <wire_name>\n");
|
||||
log(" AIGER latches to be transformed into posedge DFFs clocked by wire of");
|
||||
log(" this name (default: clk)\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
log_header(design, "Executing AIGER frontend.\n");
|
||||
|
||||
RTLIL::IdString clk_name = "\\clk";
|
||||
RTLIL::IdString module_name;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
std::string arg = args[argidx];
|
||||
if (arg == "-module_name" && argidx+1 < args.size()) {
|
||||
module_name = RTLIL::escape_id(args[++argidx]);
|
||||
continue;
|
||||
}
|
||||
if (arg == "-clk_name" && argidx+1 < args.size()) {
|
||||
clk_name = RTLIL::escape_id(args[++argidx]);
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(f, filename, args, argidx);
|
||||
|
||||
if (module_name.empty()) {
|
||||
#ifdef _WIN32
|
||||
module_name = "top"; // FIXME: basename equivalent on Win32?
|
||||
#else
|
||||
char* bn = strdup(filename.c_str());
|
||||
module_name = RTLIL::escape_id(bn);
|
||||
free(bn);
|
||||
#endif
|
||||
}
|
||||
|
||||
AigerReader reader(design, *f, module_name, clk_name);
|
||||
reader.parse_aiger();
|
||||
}
|
||||
} AigerFrontend;
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
* Eddie Hung <eddie@fpgeh.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef ABC_AIGERPARSE
|
||||
#define ABC_AIGERPARSE
|
||||
|
||||
#include "kernel/yosys.h"
|
||||
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
struct AigerReader
|
||||
{
|
||||
RTLIL::Design *design;
|
||||
std::istream &f;
|
||||
RTLIL::IdString clk_name;
|
||||
RTLIL::Module *module;
|
||||
|
||||
unsigned M, I, L, O, A;
|
||||
unsigned B, C, J, F; // Optional in AIGER 1.9
|
||||
unsigned line_count;
|
||||
|
||||
std::vector<RTLIL::Wire*> inputs;
|
||||
std::vector<RTLIL::Wire*> latches;
|
||||
std::vector<RTLIL::Wire*> outputs;
|
||||
|
||||
AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name);
|
||||
void parse_aiger();
|
||||
void parse_aiger_ascii();
|
||||
void parse_aiger_binary();
|
||||
};
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
||||
#endif
|
||||
|
|
@ -584,7 +584,7 @@ struct BlifFrontend : public Frontend {
|
|||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" read_blif [filename]\n");
|
||||
log(" read_blif [options] [filename]\n");
|
||||
log("\n");
|
||||
log("Load modules from a BLIF file into the current design.\n");
|
||||
log("\n");
|
||||
|
|
|
|||
|
|
@ -0,0 +1,5 @@
|
|||
aag 3 2 0 1 1
|
||||
2
|
||||
4
|
||||
6
|
||||
6 2 4
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
aig 3 2 0 1 1
|
||||
6
|
||||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
aag 1 1 0 1 0
|
||||
2
|
||||
2
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
aig 1 1 0 1 0
|
||||
2
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
aag 1 0 1 0 0 1
|
||||
2 3
|
||||
2
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
aig 1 0 1 0 0 1
|
||||
3
|
||||
2
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
aag 5 1 1 0 3 1
|
||||
2
|
||||
4 10
|
||||
4
|
||||
6 5 3
|
||||
8 4 2
|
||||
10 9 7
|
||||
b0 AIGER_NEVER
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
aig 5 1 1 0 3 1
|
||||
10
|
||||
4
|
||||
b0 AIGER_NEVER
|
||||
|
|
@ -0,0 +1 @@
|
|||
aag 0 0 0 0 0
|
||||
|
|
@ -0,0 +1 @@
|
|||
aig 0 0 0 0 0
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
aag 0 0 0 1 0
|
||||
0
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
aig 0 0 0 1 0
|
||||
0
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
aag 7 2 0 2 3
|
||||
2
|
||||
4
|
||||
6
|
||||
12
|
||||
6 13 15
|
||||
12 2 4
|
||||
14 3 5
|
||||
i0 x
|
||||
i1 y
|
||||
o0 s
|
||||
o1 c
|
||||
c
|
||||
half adder
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
aig 5 2 0 2 3
|
||||
10
|
||||
6
|
||||
i0 x
|
||||
i1 y
|
||||
o0 s
|
||||
o1 c
|
||||
c
|
||||
half adder
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
aag 1 1 0 1 0
|
||||
2
|
||||
3
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
aig 1 1 0 1 0
|
||||
3
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
aag 1 0 1 0 0 1
|
||||
2 3
|
||||
3
|
||||
b0 AIGER_NEVER
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
aig 1 0 1 0 0 1
|
||||
3
|
||||
3
|
||||
b0 AIGER_NEVER
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
aag 5 1 1 0 3 1
|
||||
2
|
||||
4 10
|
||||
5
|
||||
6 5 3
|
||||
8 4 2
|
||||
10 9 7
|
||||
b0 AIGER_NEVER
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
aig 5 1 1 0 3 1
|
||||
10
|
||||
5
|
||||
b0 AIGER_NEVER
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
aag 3 2 0 1 1
|
||||
2
|
||||
4
|
||||
7
|
||||
6 3 5
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
aig 3 2 0 1 1
|
||||
7
|
||||
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
#!/bin/bash
|
||||
|
||||
OPTIND=1
|
||||
seed="" # default to no seed specified
|
||||
while getopts "S:" opt
|
||||
do
|
||||
case "$opt" in
|
||||
S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
|
||||
seed="SEED=$arg" ;;
|
||||
esac
|
||||
done
|
||||
shift "$((OPTIND-1))"
|
||||
|
||||
# check for Icarus Verilog
|
||||
if ! which iverilog > /dev/null ; then
|
||||
echo "$0: Error: Icarus Verilog 'iverilog' not found."
|
||||
exit 1
|
||||
fi
|
||||
|
||||
echo "===== AAG ======"
|
||||
${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger"
|
||||
|
||||
echo "===== AIG ======"
|
||||
exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aig EXTRA_FLAGS="-f aiger"
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
aag 7 2 1 2 4
|
||||
2
|
||||
4
|
||||
6 8
|
||||
6
|
||||
7
|
||||
8 4 10
|
||||
10 13 15
|
||||
12 2 6
|
||||
14 3 7
|
||||
i0 enable
|
||||
i1 reset
|
||||
o0 Q
|
||||
o1 !Q
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
aig 7 2 1 2 4
|
||||
14
|
||||
6
|
||||
7
|
||||
i0 enable
|
||||
i1 reset
|
||||
o0 Q
|
||||
o1 !Q
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
aag 1 0 1 2 0
|
||||
2 3
|
||||
2
|
||||
3
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
aig 1 0 1 2 0
|
||||
3
|
||||
2
|
||||
3
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
aag 0 0 0 1 0
|
||||
1
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
aig 0 0 0 1 0
|
||||
1
|
||||
|
|
@ -108,8 +108,9 @@ shift $((OPTIND - 1))
|
|||
|
||||
for fn
|
||||
do
|
||||
bn=${fn%.v}
|
||||
if [ "$bn" == "$fn" ]; then
|
||||
bn=${fn%.*}
|
||||
ext=${fn##*.}
|
||||
if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
|
||||
echo "Invalid argument: $fn" >&2
|
||||
exit 1
|
||||
fi
|
||||
|
|
@ -132,8 +133,12 @@ do
|
|||
bn=$(basename $bn)
|
||||
|
||||
rm -f ${bn}_ref.fir
|
||||
|
||||
egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v
|
||||
if [[ "$ext" == "v" ]]; then
|
||||
egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
|
||||
else
|
||||
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
|
||||
frontend="verilog"
|
||||
fi
|
||||
|
||||
if [ ! -f ../${bn}_tb.v ]; then
|
||||
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
|
||||
|
|
@ -141,7 +146,8 @@ do
|
|||
cp ../${bn}_tb.v ${bn}_tb.v
|
||||
fi
|
||||
if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
|
||||
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs
|
||||
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
|
||||
"$toolsdir"/../../techlibs/common/simlib.v
|
||||
if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
|
||||
|
||||
test_count=0
|
||||
|
|
|
|||
Loading…
Reference in New Issue