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Fix initialisation of flops

This commit is contained in:
Eddie Hung 2019-06-15 09:46:35 -07:00
parent 6d74b3e004
commit a76c8a7ffd
3 changed files with 15 additions and 14 deletions
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5
passes/techmap/abc9.cc
View File

@ -520,8 +520,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
continue; continue;
} }
else if (cell->type.in("$_FF_")) { else if (cell->type.in("$_FF_")) {
SigBit D = cell->getPort("\\D"); RTLIL::Wire *D = cell->getPort("\\D").as_wire();
SigBit Q = cell->getPort("\\Q"); RTLIL::Wire *Q = cell->getPort("\\Q").as_wire();
Q->attributes.swap(D->attributes);
module->connect(Q, D); module->connect(Q, D);
it = module->cells_.erase(it); it = module->cells_.erase(it);
continue; continue;

2
techlibs/xilinx/ff_map.v
View File

@ -28,7 +28,7 @@ module \$_DFF_P_ (input D, C, output Q);
FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
`else `else
wire Q_next; wire Q_next;
\$__ABC_FDRE #(/*.INIT(|0)*/) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0)); \$__ABC_FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
\$_FF_ abc_dff (.D(Q_next), .Q(Q)); \$_FF_ abc_dff (.D(Q_next), .Q(Q));
`endif `endif
endmodule endmodule

20
techlibs/xilinx/synth_xilinx.cc
View File

@ -275,9 +275,10 @@ struct SynthXilinxPass : public ScriptPass
} }
if (check_label("map_cells")) { if (check_label("map_cells")) {
run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
if (abc == "abc9") if (abc == "abc9")
run("techmap -D _ABC -map +/xilinx/ff_map.v t:$_DFF*"); run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -D _ABC -map +/xilinx/ff_map.v");
else
run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
run("clean"); run("clean");
} }
@ -286,23 +287,22 @@ struct SynthXilinxPass : public ScriptPass
run("read_verilog -icells -lib +/xilinx/abc_ff.v"); run("read_verilog -icells -lib +/xilinx/abc_ff.v");
run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -retime" : "")); run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -retime" : ""));
} }
else if (help_mode) { else if (help_mode)
run(abc + " -luts 2:2,3,6:5,10,20 [-dff]"); run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " else
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
}
else {
run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
}
run("clean"); run("clean");
// This shregmap call infers fixed length shift registers after abc // This shregmap call infers fixed length shift registers after abc
// has performed any necessary retiming // has performed any necessary retiming
if (!nosrl || help_mode) if (!nosrl || help_mode)
run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
if (abc == "abc9")
run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"); run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
else
run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
run("clean"); run("clean");
} }