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Use analysis mode if set in file

This commit is contained in:
Miodrag Milanovic 2022-05-23 19:13:45 +02:00
parent e47cfe277e
commit a6ec5754c6
1 changed files with 2 additions and 2 deletions
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4
frontends/verific/verific.cc
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@ -2717,7 +2717,7 @@ struct VerificPass : public Pass {
if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
{
unsigned verilog_mode = veri_file::VERILOG_95; // default recommended by Verific
unsigned verilog_mode = veri_file::UNDEFINED;
bool is_formal = false;
const char* filename = nullptr;
@ -2764,7 +2764,7 @@ struct VerificPass : public Pass {
veri_file::DefineMacro("VERIFIC");
veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS");
if (!veri_file::AnalyzeMultipleFiles(file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
if (!veri_file::AnalyzeMultipleFiles(file_names, analysis_mode, work.c_str(), veri_file::MFCU)) {
verific_error_msg.clear();
log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
}