riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

coolrunner2: Insert many more required feedthrough cells

This commit is contained in:
R. Ou 2020-03-01 06:54:07 -08:00
parent 69c2d3848a
commit a6aeee4e1a
3 changed files with 217 additions and 104 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

224
techlibs/coolrunner2/coolrunner2_fixup.cc
View File

@ -23,6 +23,58 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire)
{
auto outwire = module->addWire(NEW_ID);
if (inwire == SigBit(true))
{
// Constant 1
auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", true);
xor_cell->setPort("\\OUT", outwire);
}
else if (inwire == SigBit(false))
{
// Constant 0
auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", false);
xor_cell->setPort("\\OUT", outwire);
}
else
{
auto and_to_xor_wire = module->addWire(NEW_ID);
auto and_cell = module->addCell(NEW_ID, "\\ANDTERM");
and_cell->setParam("\\TRUE_INP", 1);
and_cell->setParam("\\COMP_INP", 0);
and_cell->setPort("\\OUT", and_to_xor_wire);
and_cell->setPort("\\IN", inwire);
and_cell->setPort("\\IN_B", SigSpec());
auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", false);
xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
xor_cell->setPort("\\OUT", outwire);
}
return outwire;
}
RTLIL::Wire *makeptermbuffer(RTLIL::Module *module, SigBit inwire)
{
auto outwire = module->addWire(NEW_ID);
auto and_cell = module->addCell(NEW_ID, "\\ANDTERM");
and_cell->setParam("\\TRUE_INP", 1);
and_cell->setParam("\\COMP_INP", 0);
and_cell->setPort("\\OUT", outwire);
and_cell->setPort("\\IN", inwire);
and_cell->setPort("\\IN_B", SigSpec());
return outwire;
}
struct Coolrunner2FixupPass : public Pass { struct Coolrunner2FixupPass : public Pass {
Coolrunner2FixupPass() : Pass("coolrunner2_fixup", "insert necessary buffer cells for CoolRunner-II architecture") { } Coolrunner2FixupPass() : Pass("coolrunner2_fixup", "insert necessary buffer cells for CoolRunner-II architecture") { }
void help() YS_OVERRIDE void help() YS_OVERRIDE
@ -78,13 +130,58 @@ struct Coolrunner2FixupPass : public Pass {
} }
} }
// Start by buffering FF inputs. FF inputs can only come from either // Find all the pterm outputs
// an IO pin or from an XOR. Otherwise AND/XOR cells need to be inserted. pool<SigBit> sig_fed_by_pterm;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\ANDTERM")
{
auto output = sigmap(cell->getPort("\\OUT")[0]);
sig_fed_by_pterm.insert(output);
}
}
// Find all the bufg outputs
pool<SigBit> sig_fed_by_bufg;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\BUFG")
{
auto output = sigmap(cell->getPort("\\O")[0]);
sig_fed_by_bufg.insert(output);
}
}
// Find all the bufgsr outputs
pool<SigBit> sig_fed_by_bufgsr;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\BUFGSR")
{
auto output = sigmap(cell->getPort("\\O")[0]);
sig_fed_by_bufgsr.insert(output);
}
}
// Find all the bufgts outputs
pool<SigBit> sig_fed_by_bufgts;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\BUFGTS")
{
auto output = sigmap(cell->getPort("\\O")[0]);
sig_fed_by_bufgts.insert(output);
}
}
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N", if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE")) "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
{ {
// Buffering FF inputs. FF inputs can only come from either
// an IO pin or from an XOR. Otherwise AND/XOR cells need
// to be inserted.
SigBit input; SigBit input;
if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP")) if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
input = sigmap(cell->getPort("\\T")[0]); input = sigmap(cell->getPort("\\T")[0]);
@ -95,63 +192,116 @@ struct Coolrunner2FixupPass : public Pass {
{ {
log("Buffering input to \"%s\"\n", cell->name.c_str()); log("Buffering input to \"%s\"\n", cell->name.c_str());
auto and_to_xor_wire = module->addWire(NEW_ID); auto xor_to_ff_wire = makexorbuffer(module, input);
auto xor_to_ff_wire = module->addWire(NEW_ID);
auto and_cell = module->addCell(NEW_ID, "\\ANDTERM");
and_cell->setParam("\\TRUE_INP", 1);
and_cell->setParam("\\COMP_INP", 0);
and_cell->setPort("\\OUT", and_to_xor_wire);
and_cell->setPort("\\IN", input);
and_cell->setPort("\\IN_B", SigSpec());
auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", false);
xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
xor_cell->setPort("\\OUT", xor_to_ff_wire);
if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP")) if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
cell->setPort("\\T", xor_to_ff_wire); cell->setPort("\\T", xor_to_ff_wire);
else else
cell->setPort("\\D", xor_to_ff_wire); cell->setPort("\\D", xor_to_ff_wire);
} }
// Buffering FF clocks. FF clocks can only come from either
// a pterm or a bufg. In some cases this will be handled
// in coolrunner2_sop (e.g. if clock is generated from
// AND-ing two signals) but not in all cases.
SigBit clock;
if (cell->type.in("\\LDCP", "\\LDCP_N"))
clock = sigmap(cell->getPort("\\G")[0]);
else
clock = sigmap(cell->getPort("\\C")[0]);
if (!sig_fed_by_pterm[clock] && !sig_fed_by_bufg[clock])
{
log("Buffering clock to \"%s\"\n", cell->name.c_str());
auto pterm_to_ff_wire = makeptermbuffer(module, clock);
if (cell->type.in("\\LDCP", "\\LDCP_N"))
cell->setPort("\\G", pterm_to_ff_wire);
else
cell->setPort("\\C", pterm_to_ff_wire);
}
// Buffering FF set/reset. This can only come from either
// a pterm or a bufgsr.
SigBit set;
set = sigmap(cell->getPort("\\PRE")[0]);
if (set != SigBit(false))
{
if (!sig_fed_by_pterm[set] && !sig_fed_by_bufgsr[set])
{
log("Buffering set to \"%s\"\n", cell->name.c_str());
auto pterm_to_ff_wire = makeptermbuffer(module, set);
cell->setPort("\\PRE", pterm_to_ff_wire);
}
}
SigBit reset;
reset = sigmap(cell->getPort("\\CLR")[0]);
if (reset != SigBit(false))
{
if (!sig_fed_by_pterm[reset] && !sig_fed_by_bufgsr[reset])
{
log("Buffering reset to \"%s\"\n", cell->name.c_str());
auto pterm_to_ff_wire = makeptermbuffer(module, reset);
cell->setPort("\\CLR", pterm_to_ff_wire);
}
}
// Buffering FF clock enable
// FIXME: This doesn't fully fix PTC conflicts
// FIXME: Need to ensure constant enables are optimized out
if (cell->type.in("\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
{
SigBit ce;
ce = sigmap(cell->getPort("\\CE")[0]);
if (!sig_fed_by_pterm[ce])
{
log("Buffering clock enable to \"%s\"\n", cell->name.c_str());
auto pterm_to_ff_wire = makeptermbuffer(module, ce);
cell->setPort("\\CE", pterm_to_ff_wire);
}
}
} }
} }
// Buffer IOBUFE inputs. This can only be fed from an XOR or FF.
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (cell->type == "\\IOBUFE") if (cell->type == "\\IOBUFE")
{ {
// Buffer IOBUFE inputs. This can only be fed from an XOR or FF.
SigBit input = sigmap(cell->getPort("\\I")[0]); SigBit input = sigmap(cell->getPort("\\I")[0]);
// Special case: constant 0 and 1 are handled by xc2par
if (input == SigBit(true) || input == SigBit(false)) {
log("Not buffering constant IO to \"%s\"\n", cell->name.c_str());
continue;
}
if (!sig_fed_by_xor[input] && !sig_fed_by_ff[input]) if (!sig_fed_by_xor[input] && !sig_fed_by_ff[input])
{ {
log("Buffering input to \"%s\"\n", cell->name.c_str()); log("Buffering input to \"%s\"\n", cell->name.c_str());
auto and_to_xor_wire = module->addWire(NEW_ID); auto xor_to_io_wire = makexorbuffer(module, input);
auto xor_to_io_wire = module->addWire(NEW_ID);
auto and_cell = module->addCell(NEW_ID, "\\ANDTERM");
and_cell->setParam("\\TRUE_INP", 1);
and_cell->setParam("\\COMP_INP", 0);
and_cell->setPort("\\OUT", and_to_xor_wire);
and_cell->setPort("\\IN", input);
and_cell->setPort("\\IN_B", SigSpec());
auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", false);
xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
xor_cell->setPort("\\OUT", xor_to_io_wire);
cell->setPort("\\I", xor_to_io_wire); cell->setPort("\\I", xor_to_io_wire);
} }
// Buffer IOBUFE enables. This can only be fed from a pterm
// or a bufgts.
if (cell->hasPort("\\E"))
{
SigBit oe;
oe = sigmap(cell->getPort("\\E")[0]);
if (!sig_fed_by_pterm[oe] && !sig_fed_by_bufgts[oe])
{
log("Buffering output enable to \"%s\"\n", cell->name.c_str());
auto pterm_to_oe_wire = makeptermbuffer(module, oe);
cell->setPort("\\E", pterm_to_oe_wire);
}
}
} }
} }
} }

96
techlibs/coolrunner2/coolrunner2_sop.cc
View File

@ -108,14 +108,8 @@ struct Coolrunner2SopPass : public Pass {
} }
// Check for special P-term usage // Check for special P-term usage
bool is_special_pterm = false; bool is_special_pterm =
bool special_pterm_can_invert = false; special_pterms_no_inv.count(sop_output) || special_pterms_inv.count(sop_output);
if (special_pterms_no_inv.count(sop_output) || special_pterms_inv.count(sop_output))
{
is_special_pterm = true;
if (!special_pterms_no_inv[sop_output].size())
special_pterm_can_invert = true;
}
// Construct AND cells // Construct AND cells
pool<SigBit> intermed_wires; pool<SigBit> intermed_wires;
@ -159,53 +153,38 @@ struct Coolrunner2SopPass : public Pass {
// Special P-term handling // Special P-term handling
if (is_special_pterm) if (is_special_pterm)
{ {
if (!has_invert || special_pterm_can_invert) // Can always connect the P-term directly if it's going
// into something invert-capable
for (auto x : special_pterms_inv[sop_output])
{
std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
// If this signal is indeed inverted, flip the cell polarity
if (has_invert)
{
auto cell = std::get<0>(x);
if (cell->type == "\\FDCP") cell->type = "\\FDCP_N";
else if (cell->type == "\\FDCP_N") cell->type = "\\FDCP";
else if (cell->type == "\\FTCP") cell->type = "\\FTCP_N";
else if (cell->type == "\\FTCP_N") cell->type = "\\FTCP";
else if (cell->type == "\\FDCPE") cell->type = "\\FDCPE_N";
else if (cell->type == "\\FDCPE_N") cell->type = "\\FDCPE";
else if (cell->type == "\\LDCP") cell->type = "\\LDCP_N";
else if (cell->type == "\\LDCP_N") cell->type = "\\LDCP";
else log_assert(!"Internal error! Bad cell type!");
}
}
// If it's going into something that's not invert-capable,
// connect it directly only if this signal isn't inverted
if (!has_invert)
{ {
// Can connect the P-term directly to the special term sinks
for (auto x : special_pterms_inv[sop_output])
std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
for (auto x : special_pterms_no_inv[sop_output]) for (auto x : special_pterms_no_inv[sop_output])
std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin()); std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
} }
if (has_invert) // Otherwise, a feedthrough P-term has to be created. Leave that to happen
{ // in the coolrunner2_fixup pass.
if (special_pterm_can_invert)
{
log_assert(special_pterms_no_inv[sop_output].size() == 0);
for (auto x : special_pterms_inv[sop_output])
{
auto cell = std::get<0>(x);
// Need to invert the polarity of the cell
if (cell->type == "\\FDCP") cell->type = "\\FDCP_N";
else if (cell->type == "\\FDCP_N") cell->type = "\\FDCP";
else if (cell->type == "\\FTCP") cell->type = "\\FTCP_N";
else if (cell->type == "\\FTCP_N") cell->type = "\\FTCP";
else if (cell->type == "\\FDCPE") cell->type = "\\FDCPE_N";
else if (cell->type == "\\FDCPE_N") cell->type = "\\FDCPE";
else if (cell->type == "\\LDCP") cell->type = "\\LDCP_N";
else if (cell->type == "\\LDCP_N") cell->type = "\\LDCP";
else log_assert(!"Internal error! Bad cell type!");
}
}
else
{
// Need to construct a feed-through term
auto feedthrough_out = module->addWire(NEW_ID);
auto feedthrough_cell = module->addCell(NEW_ID, "\\ANDTERM");
feedthrough_cell->setParam("\\TRUE_INP", 1);
feedthrough_cell->setParam("\\COMP_INP", 0);
feedthrough_cell->setPort("\\OUT", feedthrough_out);
feedthrough_cell->setPort("\\IN", sop_output);
feedthrough_cell->setPort("\\IN_B", SigSpec());
for (auto x : special_pterms_inv[sop_output])
std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out);
for (auto x : special_pterms_no_inv[sop_output])
std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out);
}
}
} }
} }
else else
@ -224,23 +203,6 @@ struct Coolrunner2SopPass : public Pass {
xor_cell->setParam("\\INVERT_OUT", has_invert); xor_cell->setParam("\\INVERT_OUT", has_invert);
xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire); xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire);
xor_cell->setPort("\\OUT", sop_output); xor_cell->setPort("\\OUT", sop_output);
if (is_special_pterm)
{
// Need to construct a feed-through term
auto feedthrough_out = module->addWire(NEW_ID);
auto feedthrough_cell = module->addCell(NEW_ID, "\\ANDTERM");
feedthrough_cell->setParam("\\TRUE_INP", 1);
feedthrough_cell->setParam("\\COMP_INP", 0);
feedthrough_cell->setPort("\\OUT", feedthrough_out);
feedthrough_cell->setPort("\\IN", sop_output);
feedthrough_cell->setPort("\\IN_B", SigSpec());
for (auto x : special_pterms_inv[sop_output])
std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out);
for (auto x : special_pterms_no_inv[sop_output])
std::get<0>(x)->setPort(std::get<1>(x), feedthrough_out);
}
} }
// Finally, remove the $sop cell // Finally, remove the $sop cell

1
techlibs/coolrunner2/synth_coolrunner2.cc
View File

@ -178,6 +178,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
run("dffinit -ff LDCP Q INIT"); run("dffinit -ff LDCP Q INIT");
run("dffinit -ff LDCP_N Q INIT"); run("dffinit -ff LDCP_N Q INIT");
run("coolrunner2_sop"); run("coolrunner2_sop");
run("clean");
run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO"); run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
run("attrmvcp -attr src -attr LOC t:IOBUFE n:*"); run("attrmvcp -attr src -attr LOC t:IOBUFE n:*");
run("attrmvcp -attr src -attr LOC -driven t:IBUF n:*"); run("attrmvcp -attr src -attr LOC -driven t:IBUF n:*");