Progress in Verific bindings

frontends/verific/verific.cc

@@ -429,6 +429,8 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
 		import_attributes(wire->attributes, port);
 		module->add(wire);
 
+		wire->port_id = nl->IndexOf(port) + 1;
+
 		if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_IN)
 			wire->port_input = true;
 		if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_OUT)

tests/simple/forgen01.v

@@ -1,3 +1,6 @@
+
+// VERIFIC-SKIP
+
 module uut_forgen01(a, y);
 
 input [4:0] a;

tests/simple/mem_arst.v

@@ -10,7 +10,7 @@ module MyMem #(
   output [DataWidth-1:0] Data_o,
   input                  WR_i);
 
-  reg Data_o;
+  reg [DataWidth-1:0] Data_o;
 
   localparam Size = 2**AddrWidth;
 

tests/tools/autotest.sh

@@ -82,7 +82,7 @@ do
 	[[ "$bn" == *_tb ]] && continue
 	echo -n "Test: $bn "
 
-	rm -f ${bn}.{err,log}
+	rm -f ${bn}.{err,log,sikp}
 	mkdir -p ${bn}.out
 	rm -rf ${bn}.out/*
 
@@ -111,6 +111,11 @@ do
 			test_count=$(( test_count + 1 ))
 		}
 
+		if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP $fn; then
+			touch ../${bn}.skip
+			return
+		fi
+
 		if [ -n "$scriptfiles" ]; then
 			test_passes $fn $scriptfiles
 		elif [ -n "$scriptopt" ]; then
@@ -137,6 +142,9 @@ do
 	if [ -f ${bn}.log ]; then
 		mv ${bn}.err ${bn}.log
 		echo "-> ok"
+	elif [ -f ${bn}.skip ]; then
+		mv ${bn}.err ${bn}.skip
+		echo "-> skip"
 	else echo "-> ERROR!"; $keeprunning || exit 1; fi
 done