From a5bfb23b472966ccd55f526651c4c2b5a87db99d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 13 Mar 2024 18:19:41 +0100 Subject: [PATCH] start cleaning rams --- techlibs/nanoxplore/Makefile.inc | 5 ++- techlibs/nanoxplore/brams.txt | 26 +++++++++++++ techlibs/nanoxplore/brams_map.v | 32 ++++++++++++++++ techlibs/nanoxplore/cells_map.v | 12 ------ techlibs/nanoxplore/rf_rams_map_u.v | 12 ++++++ .../nanoxplore/{drams.txt => rf_rams_u.txt} | 0 techlibs/nanoxplore/synth_nanoxplore.cc | 37 +++++++++++++------ tests/arch/nanoxplore/lutram.ys | 4 +- 8 files changed, 101 insertions(+), 27 deletions(-) create mode 100644 techlibs/nanoxplore/brams.txt create mode 100644 techlibs/nanoxplore/brams_map.v create mode 100644 techlibs/nanoxplore/rf_rams_map_u.v rename techlibs/nanoxplore/{drams.txt => rf_rams_u.txt} (100%) diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc index ca37a2d5d..40e730cbe 100644 --- a/techlibs/nanoxplore/Makefile.inc +++ b/techlibs/nanoxplore/Makefile.inc @@ -3,6 +3,8 @@ OBJS += techlibs/nanoxplore/synth_nanoxplore.o # Techmap $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_map.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams.txt)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_l.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v)) @@ -13,5 +15,6 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v)) -$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/drams.txt)) $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_u.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt)) diff --git a/techlibs/nanoxplore/brams.txt b/techlibs/nanoxplore/brams.txt new file mode 100644 index 000000000..bc3a1722e --- /dev/null +++ b/techlibs/nanoxplore/brams.txt @@ -0,0 +1,26 @@ +ram block $__NX_RAM_ { + abits 13; + widths 1 2 4 9 per_port; + cost 64; + init no_undef; + port srsw "A" "B" { + clock anyedge; + clken; + portoption "WRITEMODE" "NORMAL" { + rdwr no_change; + } + portoption "WRITEMODE" "WRITETHROUGH" { + rdwr new; + } + portoption "WRITEMODE" "READBEFOREWRITE" { + rdwr old; + } + option "RESETMODE" "SYNC" { + rdsrst zero ungated block_wr; + } + option "RESETMODE" "ASYNC" { + rdarst zero; + } + rdinit zero; + } +} \ No newline at end of file diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v new file mode 100644 index 000000000..04b6134c3 --- /dev/null +++ b/techlibs/nanoxplore/brams_map.v @@ -0,0 +1,32 @@ +module $__NX_RAM_ (...); + +parameter INIT = 0; +parameter OPTION_RESETMODE = "SYNC"; + +parameter PORT_A_WIDTH = 9; +parameter PORT_A_CLK_POL = 1; +parameter PORT_A_OPTION_WRITEMODE = "NORMAL"; + +input PORT_A_CLK; +input PORT_A_CLK_EN; +input PORT_A_WR_EN; +input PORT_A_RD_SRST; +input PORT_A_RD_ARST; +input [12:0] PORT_A_ADDR; +input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; +output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; + +parameter PORT_B_WIDTH = 9; +parameter PORT_B_CLK_POL = 1; +parameter PORT_B_OPTION_WRITEMODE = "NORMAL"; + +input PORT_B_CLK; +input PORT_B_CLK_EN; +input PORT_B_WR_EN; +input PORT_B_RD_SRST; +input PORT_B_RD_ARST; +input [12:0] PORT_B_ADDR; +input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA; +output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA; + +endmodule \ No newline at end of file diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v index 54f2414c8..75e7140aa 100644 --- a/techlibs/nanoxplore/cells_map.v +++ b/techlibs/nanoxplore/cells_map.v @@ -70,15 +70,3 @@ module \$_SDFF_NP1_ (input D, C, R, output Q); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; NX_DFF #(.dff_ctxt(1'b0), .dff_edge(1'b1), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(1'b1)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b0), .R(R), .O(Q)); endmodule - -module $__NX_XRFB_64x18_ (input PORT_W_CLK, input [5:0] PORT_W_ADDR, PORT_R_ADDR, input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [17:0] PORT_R_RD_DATA); - parameter INIT = 1152'bx; - parameter PORT_W_CLK_POL = 1'b1; - NX_XRFB_64x18 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); -endmodule - -module $__NX_XRFB_32x36_ (input PORT_W_CLK, input [4:0] PORT_W_ADDR, PORT_R_ADDR, input [35:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [35:0] PORT_R_RD_DATA); - parameter INIT = 1152'bx; - parameter PORT_W_CLK_POL = 1'b1; - NX_XRFB_32x36 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); -endmodule diff --git a/techlibs/nanoxplore/rf_rams_map_u.v b/techlibs/nanoxplore/rf_rams_map_u.v new file mode 100644 index 000000000..397dd0fcd --- /dev/null +++ b/techlibs/nanoxplore/rf_rams_map_u.v @@ -0,0 +1,12 @@ + +module $__NX_XRFB_64x18_ (input PORT_W_CLK, input [5:0] PORT_W_ADDR, PORT_R_ADDR, input [17:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [17:0] PORT_R_RD_DATA); + parameter INIT = 1152'bx; + parameter PORT_W_CLK_POL = 1'b1; + NX_XRFB_64x18 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); +endmodule + +module $__NX_XRFB_32x36_ (input PORT_W_CLK, input [4:0] PORT_W_ADDR, PORT_R_ADDR, input [35:0] PORT_W_WR_DATA, input PORT_W_WR_EN, output [35:0] PORT_R_RD_DATA); + parameter INIT = 1152'bx; + parameter PORT_W_CLK_POL = 1'b1; + NX_XRFB_32x36 #(.mem_ctxt(INIT), .wck_edge(~PORT_W_CLK_POL)) _TECHMAP_REPLACE_ (.WCK(PORT_W_CLK), .I(PORT_W_WR_DATA), .RA(PORT_R_ADDR), .WA(PORT_W_ADDR), .WE(PORT_W_WR_EN), .WEA(1'b1), .O(PORT_R_RD_DATA)); +endmodule diff --git a/techlibs/nanoxplore/drams.txt b/techlibs/nanoxplore/rf_rams_u.txt similarity index 100% rename from techlibs/nanoxplore/drams.txt rename to techlibs/nanoxplore/rf_rams_u.txt diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 880e712c3..f6e507e62 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -73,11 +73,11 @@ struct SynthNanoXplorePass : public ScriptPass log(" -nocy\n"); log(" do not map adders to CY cells\n"); log("\n"); - log(" -nolutram\n"); - log(" do not use LUT RAM cells in output netlist\n"); + log(" -norfram\n"); + log(" do not use Register File RAM cells in output netlist\n"); log("\n"); log(" -nobram\n"); - log(" do not use block RAM cells in output netlist\n"); + log(" do not use block NX_RAM cells in output netlist\n"); log("\n"); log(" -nodsp\n"); log(" do not map multipliers to NX_DSP cells\n"); @@ -92,8 +92,8 @@ struct SynthNanoXplorePass : public ScriptPass } string top_opt, json_file, family; - bool flatten, abc9, nocy, nolutram, nobram, nodsp, iopad; - std::string postfix; + bool flatten, abc9, nocy, norfram, nobram, nodsp, iopad; + std::string postfix, rf_postfix; void clear_flags() override { @@ -103,11 +103,12 @@ struct SynthNanoXplorePass : public ScriptPass flatten = true; abc9 = false; nocy = false; - nolutram = false; + norfram = false; nobram = false; nodsp = false; iopad = false; postfix = ""; + rf_postfix = ""; } void execute(std::vector args, RTLIL::Design *design) override @@ -154,8 +155,8 @@ struct SynthNanoXplorePass : public ScriptPass nocy = true; continue; } - if (args[argidx] == "-nolutram") { - nolutram = true; + if (args[argidx] == "-norfram") { + norfram = true; continue; } if (args[argidx] == "-nobram") { @@ -177,17 +178,20 @@ struct SynthNanoXplorePass : public ScriptPass if (family.empty()) { //log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n"); family = "ultra"; - postfix = "_u"; } if (family == "ultra") { postfix = "_u"; + rf_postfix = "_u"; } else if (family == "u300") { postfix = "_u"; + rf_postfix = "_u"; } else if (family == "medium") { postfix = "_m"; + rf_postfix = "_l"; } else if (family == "large") { postfix = "_l"; + rf_postfix = "_l"; } else log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family.c_str()); @@ -238,9 +242,18 @@ struct SynthNanoXplorePass : public ScriptPass run("opt_clean"); } - if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { - run("memory_libmap -lib +/nanoxplore/drams.txt"); - run("techmap -map +/nanoxplore/cells_map.v t:$__NX_XRFB_32x36_ t:$__NX_XRFB_64x18_"); + if (check_label("map_ram")) + { + std::string args = ""; + if (nobram) + args += " -no-auto-block"; + if (norfram) + args += " -no-auto-distributed"; + if (help_mode) + args += " [-no-auto-block] [-no-auto-distributed]"; + run("memory_libmap -lib +/nanoxplore/rf_rams"+ rf_postfix+ ".txt -lib +/nanoxplore/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -norfram)"); + run("techmap -map +/nanoxplore/rf_rams_map"+ rf_postfix+ ".v -map +/nanoxplore/brams_map.v"); + run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v t:NX_XRFB* t:NX_RFB*"); } if (check_label("map_ffram")) diff --git a/tests/arch/nanoxplore/lutram.ys b/tests/arch/nanoxplore/lutram.ys index 669cb0007..9809da928 100644 --- a/tests/arch/nanoxplore/lutram.ys +++ b/tests/arch/nanoxplore/lutram.ys @@ -2,7 +2,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r synth_nanoxplore cd lutram_1w1r -select -assert-count 1 t:NX_XRFB_64x18 +select -assert-count 1 t:NX_RFB_U select -assert-count 8 t:NX_DFF -select -assert-none t:NX_XRFB_64x18 t:NX_DFF %% t:* %D +select -assert-none t:NX_RFB_U t:NX_DFF %% t:* %D