mirror of https://github.com/YosysHQ/yosys.git
fix bugs in handling last id in hdlname to scopename conversion
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d640157ec4
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@ -341,8 +341,10 @@ std::vector<IdString> parse_hdlname(const O* object)
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path.push_back("\\" + item);
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if (path.empty() && object->name.isPublic())
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path.push_back(object->name);
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if (!path.empty() && !(object->name.isPublic() || object->name.begins_with("$paramod") || object->name.begins_with("$abstract")))
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if (!path.empty() && !(object->name.isPublic() || object->name.begins_with("$paramod") || object->name.begins_with("$abstract"))) {
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path.pop_back();
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path.push_back(object->name);
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}
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return path;
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}
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@ -378,7 +378,10 @@ static void extract_fsm(RTLIL::Wire *wire)
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fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str());
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fsm_cell->attributes = wire->attributes;
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if(fsm_cell->attributes.count(ID::hdlname)) {
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fsm_cell->attributes[ID(scopename)] = fsm_cell->attributes[ID::hdlname];
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auto hdlname = fsm_cell->get_hdlname_attribute();
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hdlname.pop_back();
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fsm_cell->set_hdlname_attribute(hdlname);
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fsm_cell->set_string_attribute(ID(scopename), fsm_cell->get_string_attribute(ID::hdlname));
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fsm_cell->attributes.erase(ID::hdlname);
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}
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fsm_data.copy_to_cell(fsm_cell);
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@ -390,7 +393,10 @@ static void extract_fsm(RTLIL::Wire *wire)
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wire->name = stringf("$fsm$oldstate%s", wire->name.c_str());
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module->wires_[wire->name] = wire;
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if(wire->attributes.count(ID::hdlname)) {
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wire->attributes[ID(scopename)] = wire->attributes[ID::hdlname];
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auto hdlname = wire->get_hdlname_attribute();
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hdlname.pop_back();
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wire->set_hdlname_attribute(hdlname);
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wire->set_string_attribute(ID(scopename), wire->get_string_attribute(ID::hdlname));
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wire->attributes.erase(ID::hdlname);
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}
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