mirror of https://github.com/YosysHQ/yosys.git
Fixed handling of "input foo; reg [0:0] foo;"
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8e8e791fb5
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a588a4a5c9
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@ -186,6 +186,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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AstNode *first_node = this_wire_scope[node->str];
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AstNode *first_node = this_wire_scope[node->str];
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if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0)
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if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0)
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goto wires_are_compatible;
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goto wires_are_compatible;
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if (first_node->children.size() == 0 && node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
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AstNode *r = node->children[0];
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if (r->range_valid && r->range_left == 0 && r->range_right == 0) {
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delete r;
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node->children.pop_back();
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}
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}
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if (first_node->children.size() != node->children.size())
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if (first_node->children.size() != node->children.size())
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goto wires_are_incompatible;
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goto wires_are_incompatible;
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for (size_t j = 0; j < node->children.size(); j++) {
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for (size_t j = 0; j < node->children.size(); j++) {
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