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split latches into separate checks

This commit is contained in:
Miodrag Milanovic 2019-10-04 11:08:42 +02:00
parent 3238ee7d35
commit a5844e3ceb
2 changed files with 24 additions and 41 deletions
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34
tests/anlogic/latches.v
View File

@ -22,37 +22,3 @@ module latchsr
else if ( en ) else if ( en )
q <= d; q <= d;
endmodule endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2
);
latchp u_latchp (
.en (clk ),
.d (a ),
.q (b )
);
latchn u_latchn (
.en (clk ),
.d (a ),
.q (b1 )
);
latchsr u_latchsr (
.en (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b2 )
);
endmodule

31
tests/anlogic/latches.ys
View File

@ -2,15 +2,32 @@ read_verilog latches.v
design -save read design -save read
proc proc
async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock hierarchy -top latchp
flatten # Can't run any sort of equivalence check because latches are blown to LUTs
synth_anlogic synth_anlogic
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check cd latchp # Constrain all select calls below inside the top module
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) select -assert-count 1 t:AL_MAP_LUT3
select -assert-none t:AL_MAP_LUT3 %% t:* %D
design -load read design -load read
proc
hierarchy -top latchn
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_anlogic synth_anlogic
cd top cd latchn # Constrain all select calls below inside the top module
select -assert-count 2 t:AL_MAP_LUT3 select -assert-count 1 t:AL_MAP_LUT3
select -assert-none t:AL_MAP_LUT3 %% t:* %D
design -load read
proc
hierarchy -top latchsr
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_anlogic
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT5 select -assert-count 1 t:AL_MAP_LUT5
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT5 %% t:* %D
select -assert-none t:AL_MAP_LUT5 %% t:* %D