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Replace -ignore_redef with -[no]overwrite 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-05-03 15:25:59 +02:00
parent e060375f23
commit a572b49538
5 changed files with 58 additions and 21 deletions
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14
frontends/ast/ast.cc
View File

@ -1003,7 +1003,7 @@ static AstModule* process_module(AstNode *ast, bool defer)
// create AstModule instances for all modules in the AST tree and add them to 'design' // create AstModule instances for all modules in the AST tree and add them to 'design'
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil,
bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire) bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire)
{ {
current_ast = ast; current_ast = ast;
flag_dump_ast1 = dump_ast1; flag_dump_ast1 = dump_ast1;
@ -1042,12 +1042,20 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
(*it)->str = "$abstract" + (*it)->str; (*it)->str = "$abstract" + (*it)->str;
if (design->has((*it)->str)) { if (design->has((*it)->str)) {
if (!ignore_redef) RTLIL::Module *existing_mod = design->module((*it)->str);
if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
log_error("Re-definition of module `%s' at %s:%d!\n", log_error("Re-definition of module `%s' at %s:%d!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
log("Ignoring re-definition of module `%s' at %s:%d!\n", } else if (nooverwrite) {
log("Ignoring re-definition of module `%s' at %s:%d.\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
continue; continue;
} else {
log("Replacing existing%s module `%s' at %s:%d.\n",
existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
design->remove(existing_mod);
}
} }
design->add(process_module(*it, defer)); design->add(process_module(*it, defer));

2
frontends/ast/ast.h
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@ -275,7 +275,7 @@ namespace AST
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire); bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire);
// parametric modules are supported directly by the AST library // parametric modules are supported directly by the AST library
// therefore we need our own derivate of RTLIL::Module with overloaded virtual functions // therefore we need our own derivate of RTLIL::Module with overloaded virtual functions

32
frontends/liberty/liberty.cc
View File

@ -463,9 +463,13 @@ struct LibertyFrontend : public Frontend {
log(" -lib\n"); log(" -lib\n");
log(" only create empty blackbox modules\n"); log(" only create empty blackbox modules\n");
log("\n"); log("\n");
log(" -ignore_redef\n"); log(" -nooverwrite\n");
log(" ignore re-definitions of modules. (the default behavior is to\n"); log(" ignore re-definitions of modules. (the default behavior is to\n");
log(" create an error message.)\n"); log(" create an error message if the existing module is not a blackbox\n");
log(" module, and overwrite the existing module if it is a blackbox module.)\n");
log("\n");
log(" -overwrite\n");
log(" overwrite existing modules with the same name\n");
log("\n"); log("\n");
log(" -ignore_miss_func\n"); log(" -ignore_miss_func\n");
log(" ignore cells with missing function specification of outputs\n"); log(" ignore cells with missing function specification of outputs\n");
@ -484,7 +488,8 @@ struct LibertyFrontend : public Frontend {
virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{ {
bool flag_lib = false; bool flag_lib = false;
bool flag_ignore_redef = false; bool flag_nooverwrite = false;
bool flag_overwrite = false;
bool flag_ignore_miss_func = false; bool flag_ignore_miss_func = false;
bool flag_ignore_miss_dir = false; bool flag_ignore_miss_dir = false;
bool flag_ignore_miss_data_latch = false; bool flag_ignore_miss_data_latch = false;
@ -499,8 +504,14 @@ struct LibertyFrontend : public Frontend {
flag_lib = true; flag_lib = true;
continue; continue;
} }
if (arg == "-ignore_redef") { if (arg == "-ignore_redef" || arg == "-nooverwrite") {
flag_ignore_redef = true; flag_nooverwrite = true;
flag_overwrite = false;
continue;
}
if (arg == "-overwrite") {
flag_nooverwrite = false;
flag_overwrite = true;
continue; continue;
} }
if (arg == "-ignore_miss_func") { if (arg == "-ignore_miss_func") {
@ -537,9 +548,16 @@ struct LibertyFrontend : public Frontend {
std::string cell_name = RTLIL::escape_id(cell->args.at(0)); std::string cell_name = RTLIL::escape_id(cell->args.at(0));
if (design->has(cell_name)) { if (design->has(cell_name)) {
if (flag_ignore_redef) Module *existing_mod = design->module(cell_name);
if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
log_error("Re-definition of of cell/module %s!\n", log_id(cell_name));
} else if (flag_nooverwrite) {
log("Ignoring re-definition of module %s.\n", log_id(cell_name));
continue; continue;
log_error("Duplicate definition of cell/module %s.\n", RTLIL::unescape_id(cell_name).c_str()); } else {
log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", log_id(cell_name));
design->remove(existing_mod);
}
} }
// log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str()); // log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str());

23
frontends/verilog/verilog_frontend.cc
View File

@ -137,9 +137,13 @@ struct VerilogFrontend : public Frontend {
log(" -icells\n"); log(" -icells\n");
log(" interpret cell types starting with '$' as internal cell types\n"); log(" interpret cell types starting with '$' as internal cell types\n");
log("\n"); log("\n");
log(" -ignore_redef\n"); log(" -nooverwrite\n");
log(" ignore re-definitions of modules. (the default behavior is to\n"); log(" ignore re-definitions of modules. (the default behavior is to\n");
log(" create an error message.)\n"); log(" create an error message if the existing module is not a black box\n");
log(" module, and overwrite the existing module otherwise.)\n");
log("\n");
log(" -overwrite\n");
log(" overwrite existing modules with the same name\n");
log("\n"); log("\n");
log(" -defer\n"); log(" -defer\n");
log(" only read the abstract syntax tree and defer actual compilation\n"); log(" only read the abstract syntax tree and defer actual compilation\n");
@ -191,7 +195,8 @@ struct VerilogFrontend : public Frontend {
bool flag_nodpi = false; bool flag_nodpi = false;
bool flag_noopt = false; bool flag_noopt = false;
bool flag_icells = false; bool flag_icells = false;
bool flag_ignore_redef = false; bool flag_nooverwrite = false;
bool flag_overwrite = false;
bool flag_defer = false; bool flag_defer = false;
std::map<std::string, std::string> defines_map; std::map<std::string, std::string> defines_map;
std::list<std::string> include_dirs; std::list<std::string> include_dirs;
@ -289,8 +294,14 @@ struct VerilogFrontend : public Frontend {
flag_icells = true; flag_icells = true;
continue; continue;
} }
if (arg == "-ignore_redef") { if (arg == "-ignore_redef" || arg == "-nooverwrite") {
flag_ignore_redef = true; flag_nooverwrite = true;
flag_overwrite = false;
continue;
}
if (arg == "-overwrite") {
flag_nooverwrite = false;
flag_overwrite = true;
continue; continue;
} }
if (arg == "-defer") { if (arg == "-defer") {
@ -370,7 +381,7 @@ struct VerilogFrontend : public Frontend {
if (flag_nodpi) if (flag_nodpi)
error_on_dpi_function(current_ast); error_on_dpi_function(current_ast);
AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire); AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
if (!flag_nopp) if (!flag_nopp)
delete lexin; delete lexin;

4
passes/techmap/techmap.cc
View File

@ -933,7 +933,7 @@ struct TechmapPass : public Pass {
log(" -D <define>, -I <incdir>\n"); log(" -D <define>, -I <incdir>\n");
log(" this options are passed as-is to the Verilog frontend for loading the\n"); log(" this options are passed as-is to the Verilog frontend for loading the\n");
log(" map file. Note that the Verilog frontend is also called with the\n"); log(" map file. Note that the Verilog frontend is also called with the\n");
log(" '-ignore_redef' option set.\n"); log(" '-nooverwrite' option set.\n");
log("\n"); log("\n");
log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n"); log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
log("match cells with a type that match the text value of this attribute. Otherwise\n"); log("match cells with a type that match the text value of this attribute. Otherwise\n");
@ -1031,7 +1031,7 @@ struct TechmapPass : public Pass {
simplemap_get_mappers(worker.simplemap_mappers); simplemap_get_mappers(worker.simplemap_mappers);
std::vector<std::string> map_files; std::vector<std::string> map_files;
std::string verilog_frontend = "verilog -ignore_redef"; std::string verilog_frontend = "verilog -nooverwrite";
int max_iter = -1; int max_iter = -1;
size_t argidx; size_t argidx;