mirror of https://github.com/YosysHQ/yosys.git
proc_arst: Add special-casing of clock signal in conditionals.
The already-existing special case for conditionals on clock has been remade as follows: - now triggered for the last remaining edge trigger after all others have been converted to async reset, not just when there is only one sync rule in the first place - does not require all contained assignments to be constant, as opposed to a reset conditional — merely const-folds the condition In addition, the code has been refactored a bit; as a bonus, the priority order of async resets found is now preserved in resulting sync rule ordering (though this is not yet respected by proc_dff). Fixes #2656.
This commit is contained in:
Marcelina Kościelnicka
parent
3af871f969
commit
a55bf6375b
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@ -179,39 +179,67 @@ RTLIL::SigSpec apply_reset(RTLIL::Module *mod, RTLIL::Process *proc, RTLIL::Sync
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void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map)
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{
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restart_proc_arst:
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if (proc->root_case.switches.size() != 1)
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return;
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RTLIL::SigSpec root_sig = proc->root_case.switches[0]->signal;
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std::vector<RTLIL::SyncRule *> arst_syncs;
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std::vector<RTLIL::SyncRule *> edge_syncs;
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std::vector<RTLIL::SyncRule *> other_syncs;
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for (auto &sync : proc->syncs) {
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if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) {
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if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) {
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arst_syncs.push_back(sync);
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} else if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) {
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edge_syncs.push_back(sync);
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} else {
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other_syncs.push_back(sync);
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}
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}
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bool did_something = false;
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while (proc->root_case.switches.size() == 1) {
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RTLIL::SigSpec root_sig = proc->root_case.switches[0]->signal;
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bool found = false;
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for (auto it = edge_syncs.begin(); it != edge_syncs.end(); ++it) {
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auto sync = *it;
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bool polarity = sync->type == RTLIL::SyncType::STp;
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if (check_signal(mod, root_sig, sync->signal, polarity)) {
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if (proc->syncs.size() == 1) {
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log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str());
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} else {
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if (edge_syncs.size() > 1) {
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log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str());
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sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0;
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}
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for (auto &action : sync->actions) {
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action.second = apply_reset(mod, proc, sync, assign_map, root_sig, polarity, action.second, action.first);
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}
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for (auto &memwr : sync->mem_write_actions) {
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RTLIL::SigSpec en = apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.enable, memwr.enable);
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if (!en.is_fully_zero()) {
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log_error("Async reset %s causes memory write to %s.\n",
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log_signal(sync->signal), log_id(memwr.memid));
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arst_syncs.push_back(sync);
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edge_syncs.erase(it);
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for (auto &action : sync->actions) {
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action.second = apply_reset(mod, proc, sync, assign_map, root_sig, polarity, action.second, action.first);
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}
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apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.address, memwr.address);
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apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.data, memwr.data);
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for (auto &memwr : sync->mem_write_actions) {
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RTLIL::SigSpec en = apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.enable, memwr.enable);
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if (!en.is_fully_zero()) {
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log_error("Async reset %s causes memory write to %s.\n",
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log_signal(sync->signal), log_id(memwr.memid));
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}
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apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.address, memwr.address);
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apply_reset(mod, proc, sync, assign_map, root_sig, polarity, memwr.data, memwr.data);
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}
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sync->mem_write_actions.clear();
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eliminate_const(mod, &proc->root_case, root_sig, polarity);
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} else {
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log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name.c_str(), proc->name.c_str());
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eliminate_const(mod, &proc->root_case, root_sig, !polarity);
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}
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sync->mem_write_actions.clear();
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eliminate_const(mod, &proc->root_case, root_sig, polarity);
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goto restart_proc_arst;
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did_something = true;
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found = true;
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break;
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}
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}
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if (!found)
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break;
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}
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if (did_something) {
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proc->syncs.clear();
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proc->syncs.insert(proc->syncs.end(), arst_syncs.begin(), arst_syncs.end());
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proc->syncs.insert(proc->syncs.end(), edge_syncs.begin(), edge_syncs.end());
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proc->syncs.insert(proc->syncs.end(), other_syncs.begin(), other_syncs.end());
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}
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}
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@ -0,0 +1,31 @@
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read_verilog <<EOT
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module top (...);
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input clk, rst, d1, d2;
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output q1, q2;
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always @(posedge clk)
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if (clk)
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q1 <= d1;
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always @(posedge clk, posedge rst)
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if (rst)
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q2 <= 0;
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else if (clk)
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q2 <= d2;
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endmodule
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EOT
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proc
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opt
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select -assert-count 1 t:$dff
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select -assert-count 1 w:clk %a %co t:$dff %i
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select -assert-count 1 w:d1 %a %co t:$dff %i
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select -assert-count 1 w:q1 %a %ci t:$dff %i
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select -assert-count 1 t:$adff
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select -assert-count 1 w:clk %a %co t:$adff %i
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select -assert-count 1 w:rst %a %co t:$adff %i
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select -assert-count 1 w:d2 %a %co t:$adff %i
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select -assert-count 1 w:q2 %a %ci t:$adff %i
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