mirror of https://github.com/YosysHQ/yosys.git
Cosmetic fixes in "hierarchy" for blackbox modules
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3216f9420e
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@ -268,7 +268,7 @@ void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &used, RTL
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if (indent == 0)
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if (indent == 0)
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log("Top module: %s\n", mod->name.c_str());
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log("Top module: %s\n", mod->name.c_str());
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else
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else if (!mod->get_bool_attribute("\\blackbox"))
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log("Used module: %*s%s\n", indent, "", mod->name.c_str());
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log("Used module: %*s%s\n", indent, "", mod->name.c_str());
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used.insert(mod);
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used.insert(mod);
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@ -295,6 +295,7 @@ void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, bool f
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if (used.count(it.second) == 0)
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if (used.count(it.second) == 0)
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del_modules.push_back(it.second);
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del_modules.push_back(it.second);
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int del_counter = 0;
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for (auto mod : del_modules) {
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for (auto mod : del_modules) {
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if (first_pass && mod->name.substr(0, 9) == "$abstract")
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if (first_pass && mod->name.substr(0, 9) == "$abstract")
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continue;
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continue;
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@ -302,10 +303,11 @@ void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, bool f
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continue;
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continue;
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log("Removing unused module `%s'.\n", mod->name.c_str());
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log("Removing unused module `%s'.\n", mod->name.c_str());
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design->modules_.erase(mod->name);
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design->modules_.erase(mod->name);
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del_counter++;
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delete mod;
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delete mod;
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}
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}
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log("Removed %d unused modules.\n", GetSize(del_modules));
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log("Removed %d unused modules.\n", del_counter);
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}
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}
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bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
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bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
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