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Extend test with renaming cells with prefix too

This commit is contained in:
Eddie Hung 2019-10-02 12:43:18 -07:00
parent 369652d4b9
commit a4f2f7d23c
1 changed files with 2 additions and 0 deletions
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tests/techmap/techmap_replace.ys
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@ -2,6 +2,7 @@ read_verilog <<EOT
module sub(input i, output o, input j); module sub(input i, output o, input j);
foobar _TECHMAP_REPLACE_(i, o, j); foobar _TECHMAP_REPLACE_(i, o, j);
wire _TECHMAP_REPLACE_.asdf = i ; wire _TECHMAP_REPLACE_.asdf = i ;
barfoo _TECHMAP_REPLACE_.blah (i, o, j);
endmodule endmodule
EOT EOT
design -stash techmap design -stash techmap
@ -14,3 +15,4 @@ EOT
techmap -map %techmap techmap -map %techmap
select -assert-any w:s0.asdf select -assert-any w:s0.asdf
select -assert-any c:s0.blah