Added tests/realmath to "make test"

This commit is contained in:
Clifford Wolf 2014-06-15 09:31:03 +02:00
parent 4d1df128fa
commit a4ec19c25c
5 changed files with 6 additions and 4 deletions

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@ -161,6 +161,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
cd tests/simple && bash run-test.sh cd tests/simple && bash run-test.sh
cd tests/hana && bash run-test.sh cd tests/hana && bash run-test.sh
cd tests/asicworld && bash run-test.sh cd tests/asicworld && bash run-test.sh
cd tests/realmath && bash run-test.sh
cd tests/techmap && bash run-test.sh cd tests/techmap && bash run-test.sh
cd tests/sat && bash run-test.sh cd tests/sat && bash run-test.sh

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@ -1,3 +1,2 @@
#!/bin/bash #!/bin/bash
make -C ../.. || exit 1
exec bash ../tools/autotest.sh *.v exec bash ../tools/autotest.sh *.v

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@ -1,3 +1,2 @@
#!/bin/bash #!/bin/bash
make -C ../.. || exit 1
exec bash ../tools/autotest.sh -l hana_vlib.v test_*.v exec bash ../tools/autotest.sh -l hana_vlib.v test_*.v

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@ -13,7 +13,11 @@ for ((i = 0; i < 100; i++)); do
idx=$( printf "%05d" $i ) idx=$( printf "%05d" $i )
../../../yosys -q uut_${idx}.ys ../../../yosys -q uut_${idx}.ys
iverilog -o uut_${idx}_tb uut_${idx}_tb.v uut_${idx}.v uut_${idx}_syn.v iverilog -o uut_${idx}_tb uut_${idx}_tb.v uut_${idx}.v uut_${idx}_syn.v
./uut_${idx}_tb ./uut_${idx}_tb | tee uut_${idx}.err
if test -s uut_${idx}.err; then
exit 1
fi
rm -f uut_${idx}.err
done done
echo echo

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@ -6,5 +6,4 @@ if ! which iverilog > /dev/null ; then
exit 1 exit 1
fi fi
make -C ../.. || exit 1
exec bash ../tools/autotest.sh *.v exec bash ../tools/autotest.sh *.v