mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3986 from povik/sim-ui-fixes
Slightly improve `sim` UI
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commit
a4951a3a97
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@ -219,9 +219,13 @@ struct SimInstance
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log_assert(module);
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log_assert(module);
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if (module->get_blackbox_attribute(true))
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if (module->get_blackbox_attribute(true))
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log_error("Cannot simulate blackbox module %s (instanced at %s).\n",
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log_error("Cannot simulate blackbox module %s (instantiated at %s).\n",
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log_id(module->name), hiername().c_str());
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log_id(module->name), hiername().c_str());
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if (module->has_processes())
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log_error("Found processes in simulation hierarchy (in module %s at %s). Run 'proc' first.\n",
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log_id(module), hiername().c_str());
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if (parent) {
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if (parent) {
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log_assert(parent->children.count(instance) == 0);
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log_assert(parent->children.count(instance) == 0);
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parent->children[instance] = this;
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parent->children[instance] = this;
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@ -579,7 +583,7 @@ struct SimInstance
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Const data = Const(State::Sx, mem.width << port.wide_log2);
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Const data = Const(State::Sx, mem.width << port.wide_log2);
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if (port.clk_enable)
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if (port.clk_enable)
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log_error("Memory %s.%s has clocked read ports. Run 'memory' with -nordff.\n", log_id(module), log_id(mem.memid));
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log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", log_id(module), log_id(mem.memid));
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if (addr.is_fully_def()) {
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if (addr.is_fully_def()) {
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int addr_int = addr.as_int();
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int addr_int = addr.as_int();
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