Merge pull request #1270 from YosysHQ/eddie/alu_lcu_doc

Add a few comments to document $alu and $lcu

techlibs/common/simlib.v

@@ -532,14 +532,26 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $lcu (P, G, CI, CO)
+//-
+//- Lookahead carry unit
+//- A building block dedicated to fast computation of carry-bits used in binary
+//- arithmetic operations. By replacing the ripple carry structure used in full-adder
+//- blocks, the more significant  bits of the sum can be expected to be computed more
+//- quickly.
+//- Typically created during `techmap` of $alu cells (see the "_90_alu" rule in
+//- +/techmap.v).
 module \$lcu (P, G, CI, CO);
 
 parameter WIDTH = 1;
 
-input [WIDTH-1:0] P, G;
+input [WIDTH-1:0] P;    // Propagate
-input CI;
+input [WIDTH-1:0] G;    // Generate
+input CI;               // Carry-in
 
-output reg [WIDTH-1:0] CO;
+output reg [WIDTH-1:0] CO; // Carry-out
 
 integer i;
 always @* begin
@@ -555,6 +567,17 @@ endmodule
 
 // --------------------------------------------------------
 
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $alu (A, B, CI, BI, X, Y, CO)
+//-
+//- Arithmetic logic unit.
+//- A building block supporting both binary addition/subtraction operations, and
+//- indirectly, comparison operations.
+//- Typically created by the `alumacc` pass, which transforms:
+//-   $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex
+//- cells into this $alu cell.
+//-
 module \$alu (A, B, CI, BI, X, Y, CO);
 
 parameter A_SIGNED = 0;
@@ -563,12 +586,16 @@ parameter A_WIDTH = 1;
 parameter B_WIDTH = 1;
 parameter Y_WIDTH = 1;
 
-input [A_WIDTH-1:0] A;
+input [A_WIDTH-1:0] A;      // Input operand
-input [B_WIDTH-1:0] B;
+input [B_WIDTH-1:0] B;      // Input operand
-output [Y_WIDTH-1:0] X, Y;
+output [Y_WIDTH-1:0] X;     // A xor B (sign-extended, optional B inversion,
+                            //          used in combination with
+                            //          reduction-AND for $eq/$ne ops)
+output [Y_WIDTH-1:0] Y;     // Sum
 
-input CI, BI;
+input CI;                   // Carry-in (set for $sub)
-output [Y_WIDTH-1:0] CO;
+input BI;                   // Invert-B (set for $sub)
+output [Y_WIDTH-1:0] CO;    // Carry-out
 
 wire [Y_WIDTH-1:0] AA, BB;
 
@@ -584,6 +611,7 @@ endgenerate
 wire y_co_undef = ^{A, A, B, B, CI, CI, BI, BI};
 
 assign X = AA ^ BB;
+// Full adder
 assign Y = (AA + BB + CI) ^ {Y_WIDTH{y_co_undef}};
 
 function get_carry;