riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #3990 from zeldin/deterministic_scc

This commit is contained in:
N. Engelhardt 2023-10-16 16:51:54 +02:00 committed by GitHub
parent edee11bcc1 0ca39e233b
commit a2f59cf911
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 13 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
passes/cmds/scc.cc
View File

@ -27,7 +27,6 @@
#include "kernel/log.h" #include "kernel/log.h"
#include <stdlib.h> #include <stdlib.h>
#include <stdio.h> #include <stdio.h>
#include <set>
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
@ -39,18 +38,18 @@ struct SccWorker
SigMap sigmap; SigMap sigmap;
CellTypes ct, specifyCells; CellTypes ct, specifyCells;
std::set<RTLIL::Cell*> workQueue; pool<RTLIL::Cell*> workQueue;
std::map<RTLIL::Cell*, std::set<RTLIL::Cell*>> cellToNextCell; dict<RTLIL::Cell*, pool<RTLIL::Cell*>> cellToNextCell;
std::map<RTLIL::Cell*, RTLIL::SigSpec> cellToPrevSig, cellToNextSig; dict<RTLIL::Cell*, RTLIL::SigSpec> cellToPrevSig, cellToNextSig;
std::map<RTLIL::Cell*, std::pair<int, int>> cellLabels; dict<RTLIL::Cell*, std::pair<int, int>> cellLabels;
std::map<RTLIL::Cell*, int> cellDepth; dict<RTLIL::Cell*, int> cellDepth;
std::set<RTLIL::Cell*> cellsOnStack; pool<RTLIL::Cell*> cellsOnStack;
std::vector<RTLIL::Cell*> cellStack; std::vector<RTLIL::Cell*> cellStack;
int labelCounter; int labelCounter;
std::map<RTLIL::Cell*, int> cell2scc; dict<RTLIL::Cell*, int> cell2scc;
std::vector<std::set<RTLIL::Cell*>> sccList; std::vector<pool<RTLIL::Cell*>> sccList;
void run(RTLIL::Cell *cell, int depth, int maxDepth) void run(RTLIL::Cell *cell, int depth, int maxDepth)
{ {
@ -85,7 +84,7 @@ struct SccWorker
else else
{ {
log("Found an SCC:"); log("Found an SCC:");
std::set<RTLIL::Cell*> scc; pool<RTLIL::Cell*> scc;
while (cellsOnStack.count(cell) > 0) { while (cellsOnStack.count(cell) > 0) {
RTLIL::Cell *c = cellStack.back(); RTLIL::Cell *c = cellStack.back();
cellStack.pop_back(); cellStack.pop_back();
@ -199,11 +198,11 @@ struct SccWorker
for (auto cell : workQueue) for (auto cell : workQueue)
{ {
cellToNextCell[cell] = sigToNextCells.find(cellToNextSig[cell]); sigToNextCells.find(cellToNextSig[cell], cellToNextCell[cell]);
if (!nofeedbackMode && cellToNextCell[cell].count(cell)) { if (!nofeedbackMode && cellToNextCell[cell].count(cell)) {
log("Found an SCC:"); log("Found an SCC:");
std::set<RTLIL::Cell*> scc; pool<RTLIL::Cell*> scc;
log(" %s", RTLIL::id2cstr(cell->name)); log(" %s", RTLIL::id2cstr(cell->name));
cell2scc[cell] = sccList.size(); cell2scc[cell] = sccList.size();
scc.insert(cell); scc.insert(cell);
@ -231,7 +230,7 @@ struct SccWorker
{ {
for (int i = 0; i < int(sccList.size()); i++) for (int i = 0; i < int(sccList.size()); i++)
{ {
std::set<RTLIL::Cell*> &cells = sccList[i]; pool<RTLIL::Cell*> &cells = sccList[i];
RTLIL::SigSpec prevsig, nextsig, sig; RTLIL::SigSpec prevsig, nextsig, sig;
for (auto cell : cells) { for (auto cell : cells) {
@ -295,7 +294,7 @@ struct SccPass : public Pass {
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {
std::map<std::string, std::string> setAttr; dict<std::string, std::string> setAttr;
bool allCellTypes = false; bool allCellTypes = false;
bool selectMode = false; bool selectMode = false;
bool nofeedbackMode = false; bool nofeedbackMode = false;