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abc -> abc9

This commit is contained in:
Eddie Hung 2019-10-04 17:56:38 -07:00
parent f0cadb0de8
commit a2ef93f03a
1 changed files with 3 additions and 3 deletions
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6
techlibs/xilinx/synth_xilinx.cc
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@ -481,13 +481,13 @@ struct SynthXilinxPass : public ScriptPass
"will use timing for 'xc7' instead.\n", family.c_str()); "will use timing for 'xc7' instead.\n", family.c_str());
run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
run("read_verilog -icells -lib +/xilinx/abc9_model.v"); run("read_verilog -icells -lib +/xilinx/abc9_model.v");
std::string abc9_opts = " -box +/xilinx/abc_xc7.box"; std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
abc9_opts += " -nomfs"; abc9_opts += " -nomfs";
if (nowidelut) if (nowidelut)
abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut"; abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
else else
abc9_opts += " -lut +/xilinx/abc_xc7.lut"; abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
run("abc9" + abc9_opts); run("abc9" + abc9_opts);
} }
else { else {