mirror of https://github.com/YosysHQ/yosys.git
xilinx: Add xilinx_dffopt pass (#1557)
This commit is contained in:
Marcin Kościelnicki
parent
aff6ad1ce0
commit
a235250403
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@ -55,6 +55,7 @@ Yosys 0.9 .. Yosys 0.9-dev
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- Added "check -mapped"
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- Added checking of SystemVerilog always block types (always_comb,
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always_latch and always_ff)
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- Added "xilinx_dffopt" pass
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Yosys 0.8 .. Yosys 0.9
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----------------------
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@ -44,6 +44,10 @@ struct EquivOptPass:public ScriptPass
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log(" expand the modules in this file before proving equivalence. this is\n");
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log(" useful for handling architecture-specific primitives.\n");
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log("\n");
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log(" -blacklist <file>\n");
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log(" Do not match cells or signals that match the names in the file\n");
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log(" (passed to equiv_make).\n");
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log("\n");
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log(" -assert\n");
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log(" produce an error if the circuits are not equivalent.\n");
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log("\n");
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@ -61,13 +65,14 @@ struct EquivOptPass:public ScriptPass
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log("\n");
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}
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std::string command, techmap_opts;
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std::string command, techmap_opts, make_opts;
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bool assert, undef, multiclock, async2sync;
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void clear_flags() YS_OVERRIDE
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{
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command = "";
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techmap_opts = "";
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make_opts = "";
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assert = false;
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undef = false;
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multiclock = false;
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@ -93,6 +98,10 @@ struct EquivOptPass:public ScriptPass
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techmap_opts += " -map " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-blacklist" && argidx + 1 < args.size()) {
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make_opts += " -blacklist " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-assert") {
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assert = true;
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continue;
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@ -170,7 +179,12 @@ struct EquivOptPass:public ScriptPass
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run("clk2fflogic", "(only with -multiclock)");
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if (async2sync || help_mode)
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run("async2sync", " (only with -async2sync)");
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run("equiv_make gold gate equiv");
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string opts;
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if (help_mode)
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opts = " -blacklist <filename> ...";
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else
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opts = make_opts;
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run("equiv_make" + opts + " gold gate equiv");
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if (help_mode)
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run("equiv_induct [-undef] equiv");
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else if (undef)
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@ -1,5 +1,6 @@
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OBJS += techlibs/xilinx/synth_xilinx.o
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OBJS += techlibs/xilinx/xilinx_dffopt.o
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GENFILES += techlibs/xilinx/brams_init_36.vh
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GENFILES += techlibs/xilinx/brams_init_32.vh
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@ -329,6 +329,41 @@ module FDSE (
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endcase endgenerate
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endmodule
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module FDRSE (
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output reg Q,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_C_INVERTED" *)
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input C,
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(* invertible_pin = "IS_CE_INVERTED" *)
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input CE,
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(* invertible_pin = "IS_D_INVERTED" *)
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input D,
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(* invertible_pin = "IS_R_INVERTED" *)
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input R,
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(* invertible_pin = "IS_S_INVERTED" *)
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input S
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);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_CE_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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parameter [0:0] IS_S_INVERTED = 1'b0;
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initial Q <= INIT;
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wire c = C ^ IS_C_INVERTED;
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wire ce = CE ^ IS_CE_INVERTED;
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wire d = D ^ IS_D_INVERTED;
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wire r = R ^ IS_R_INVERTED;
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wire s = S ^ IS_S_INVERTED;
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always @(posedge c)
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if (r)
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Q <= 0;
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else if (s)
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Q <= 1;
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else if (ce)
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Q <= d;
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endmodule
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module FDCE (
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(* abc9_arrival=303 *)
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output reg Q,
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@ -66,7 +66,7 @@ CELLS = [
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# CLB -- registers/latches.
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# Virtex 1/2/4/5, Spartan 3.
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Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}),
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Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}),
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# Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}),
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Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}),
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# Virtex 6, Spartan 6, Series 7, Ultrascale.
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# Cell('FDCE'),
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@ -17,27 +17,6 @@ module FDCPE (...);
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input PRE;
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endmodule
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module FDRSE (...);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_CE_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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parameter [0:0] IS_S_INVERTED = 1'b0;
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output Q;
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(* clkbuf_sink *)
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(* invertible_pin = "IS_C_INVERTED" *)
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input C;
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(* invertible_pin = "IS_CE_INVERTED" *)
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input CE;
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(* invertible_pin = "IS_D_INVERTED" *)
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input D;
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(* invertible_pin = "IS_R_INVERTED" *)
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input R;
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(* invertible_pin = "IS_S_INVERTED" *)
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input S;
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endmodule
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module LDCPE (...);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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@ -570,6 +570,7 @@ struct SynthXilinxPass : public ScriptPass
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else
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techmap_args += " -map " + ff_map_file;
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run("techmap " + techmap_args);
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run("xilinx_dffopt");
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run("clean");
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}
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@ -0,0 +1,351 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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typedef std::pair<Const, std::vector<SigBit>> LutData;
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// Compute a LUT implementing (select ^ select_inv) ? alt_data : data. Returns true if successful.
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bool merge_lut(LutData &result, const LutData &data, const LutData select, bool select_inv, SigBit alt_data, int max_lut_size) {
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// First, gather input signals.
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result.second = data.second;
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int idx_alt = -1;
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if (alt_data.wire) {
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// Check if we already have it.
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for (int i = 0; i < GetSize(result.second); i++)
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if (result.second[i] == alt_data)
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idx_alt = i;
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// If not, add it.
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if (idx_alt == -1) {
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idx_alt = GetSize(result.second);
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result.second.push_back(alt_data);
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}
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}
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std::vector<int> idx_sel;
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for (auto bit : select.second) {
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int idx = -1;
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for (int i = 0; i < GetSize(result.second); i++)
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if (result.second[i] == bit)
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idx = i;
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if (idx == -1) {
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idx = GetSize(result.second);
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result.second.push_back(bit);
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}
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idx_sel.push_back(idx);
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}
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// If LUT would be too large, bail.
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if (GetSize(result.second) > max_lut_size)
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return false;
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// Okay, we're doing it — compute the LUT mask.
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result.first = Const(0, 1 << GetSize(result.second));
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for (int i = 0; i < GetSize(result.first); i++) {
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int sel_lut_idx = 0;
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for (int j = 0; j < GetSize(select.second); j++)
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if (i & 1 << idx_sel[j])
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sel_lut_idx |= 1 << j;
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bool select_val = (select.first.bits[sel_lut_idx] == State::S1);
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bool new_bit;
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if (select_val ^ select_inv) {
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// Use alt_data.
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if (alt_data.wire)
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new_bit = (i & 1 << idx_alt) != 0;
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else
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new_bit = alt_data.data == State::S1;
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} else {
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// Use original LUT.
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int lut_idx = i & ((1 << GetSize(data.second)) - 1);
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new_bit = data.first.bits[lut_idx] == State::S1;
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}
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result.first.bits[i] = new_bit ? State::S1 : State::S0;
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}
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return true;
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}
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struct XilinxDffOptPass : public Pass {
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XilinxDffOptPass() : Pass("xilinx_dffopt", "Xilinx: optimize FF control signal usage") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" xilinx_dffopt [options] [selection]\n");
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log("\n");
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log("Converts hardware clock enable and set/reset signals on FFs to emulation\n");
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log("using LUTs, if doing so would improve area. Operates on post-techmap Xilinx\n");
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log("cells (LUT*, FD*).\n");
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log("\n");
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log(" -lut4\n");
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log(" Assume a LUT4-based device (instead of a LUT6-based device).\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing XILINX_DFFOPT pass (optimize FF control signal usage).\n");
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size_t argidx;
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int max_lut_size = 6;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-lut4") {
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max_lut_size = 4;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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log("Optimizing FFs in %s.\n", log_id(module));
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SigMap sigmap(module);
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dict<SigBit, pair<LutData, Cell *>> bit_to_lut;
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dict<SigBit, int> bit_uses;
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// Gather LUTs.
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for (auto cell : module->selected_cells())
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{
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for (auto port : cell->connections())
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for (auto bit : port.second)
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bit_uses[sigmap(bit)]++;
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if (cell->get_bool_attribute(ID::keep))
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continue;
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if (cell->type == ID(INV)) {
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SigBit sigout = sigmap(cell->getPort(ID(O)));
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SigBit sigin = sigmap(cell->getPort(ID(I)));
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bit_to_lut[sigout] = make_pair(LutData(Const(1, 2), {sigin}), cell);
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} else if (cell->type.in(ID(LUT1), ID(LUT2), ID(LUT3), ID(LUT4), ID(LUT5), ID(LUT6))) {
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SigBit sigout = sigmap(cell->getPort(ID(O)));
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const Const &init = cell->getParam(ID(INIT));
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std::vector<SigBit> sigin;
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sigin.push_back(sigmap(cell->getPort(ID(I0))));
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if (cell->type == ID(LUT1))
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goto lut_sigin_done;
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sigin.push_back(sigmap(cell->getPort(ID(I1))));
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if (cell->type == ID(LUT2))
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goto lut_sigin_done;
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sigin.push_back(sigmap(cell->getPort(ID(I2))));
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if (cell->type == ID(LUT3))
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goto lut_sigin_done;
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sigin.push_back(sigmap(cell->getPort(ID(I3))));
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if (cell->type == ID(LUT4))
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goto lut_sigin_done;
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sigin.push_back(sigmap(cell->getPort(ID(I4))));
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if (cell->type == ID(LUT5))
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goto lut_sigin_done;
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sigin.push_back(sigmap(cell->getPort(ID(I5))));
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lut_sigin_done:
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bit_to_lut[sigout] = make_pair(LutData(init, sigin), cell);
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}
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}
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for (auto wire : module->wires())
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if (wire->port_output || wire->port_input)
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for (int i = 0; i < GetSize(wire); i++)
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bit_uses[sigmap(SigBit(wire, i))]++;
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// Iterate through FFs.
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for (auto cell : module->selected_cells())
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{
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bool has_s = false, has_r = false;
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if (cell->type.in(ID(FDCE), ID(FDPE), ID(FDCPE), ID(FDCE_1), ID(FDPE_1), ID(FDCPE_1))) {
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// Async reset.
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} else if (cell->type.in(ID(FDRE), ID(FDRE_1))) {
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has_r = true;
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} else if (cell->type.in(ID(FDSE), ID(FDSE_1))) {
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has_s = true;
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} else if (cell->type.in(ID(FDRSE), ID(FDRSE_1))) {
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has_r = true;
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has_s = true;
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} else {
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// Not a FF.
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continue;
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}
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if (cell->get_bool_attribute(ID::keep))
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continue;
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// Don't bother if D has more than one use.
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SigBit sig_D = sigmap(cell->getPort(ID(D)));
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if (bit_uses[sig_D] > 2)
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continue;
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// Find the D LUT.
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auto it_D = bit_to_lut.find(sig_D);
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if (it_D == bit_to_lut.end())
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continue;
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LutData lut_d = it_D->second.first;
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Cell *cell_d = it_D->second.second;
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if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) {
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// Flip all bits in the LUT.
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for (int i = 0; i < GetSize(lut_d.first); i++)
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lut_d.first.bits[i] = (lut_d.first.bits[i] == State::S1) ? State::S0 : State::S1;
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}
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LutData lut_d_post_ce;
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LutData lut_d_post_s;
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LutData lut_d_post_r;
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bool worthy_post_ce = false;
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bool worthy_post_s = false;
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bool worthy_post_r = false;
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// First, unmap CE.
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SigBit sig_Q = sigmap(cell->getPort(ID(Q)));
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SigBit sig_CE = sigmap(cell->getPort(ID(CE)));
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LutData lut_ce = LutData(Const(2, 2), {sig_CE});
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auto it_CE = bit_to_lut.find(sig_CE);
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if (it_CE != bit_to_lut.end())
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lut_ce = it_CE->second.first;
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if (sig_CE.wire) {
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// Merge CE LUT and D LUT into one. If it cannot be done, nothing to do about this FF.
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if (!merge_lut(lut_d_post_ce, lut_d, lut_ce, true, sig_Q, max_lut_size))
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continue;
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// If this gets rid of a CE LUT, it's worth it. If not, it still may be worth it, if we can remove set/reset as well.
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if (it_CE != bit_to_lut.end())
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worthy_post_ce = true;
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} else if (sig_CE.data != State::S1) {
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// Strange. Should not happen in a reasonable flow, so bail.
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continue;
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} else {
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lut_d_post_ce = lut_d;
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}
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// Second, unmap S, if any.
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lut_d_post_s = lut_d_post_ce;
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if (has_s) {
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SigBit sig_S = sigmap(cell->getPort(ID(S)));
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LutData lut_s = LutData(Const(2, 2), {sig_S});
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bool inv_s = cell->hasParam(ID(IS_S_INVERTED)) && cell->getParam(ID(IS_S_INVERTED)).as_bool();
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auto it_S = bit_to_lut.find(sig_S);
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if (it_S != bit_to_lut.end())
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lut_s = it_S->second.first;
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if (sig_S.wire) {
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// Merge S LUT and D LUT into one. If it cannot be done, try to at least merge CE.
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if (!merge_lut(lut_d_post_s, lut_d_post_ce, lut_s, inv_s, SigBit(State::S1), max_lut_size))
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goto unmap;
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// If this gets rid of an S LUT, it's worth it.
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if (it_S != bit_to_lut.end())
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worthy_post_s = true;
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} else if (sig_S.data != (inv_s ? State::S1 : State::S0)) {
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// Strange. Should not happen in a reasonable flow, so bail.
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continue;
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||||
}
|
||||
}
|
||||
|
||||
// Third, unmap R, if any.
|
||||
lut_d_post_r = lut_d_post_s;
|
||||
if (has_r) {
|
||||
SigBit sig_R = sigmap(cell->getPort(ID(R)));
|
||||
LutData lut_r = LutData(Const(2, 2), {sig_R});
|
||||
bool inv_r = cell->hasParam(ID(IS_R_INVERTED)) && cell->getParam(ID(IS_R_INVERTED)).as_bool();
|
||||
auto it_R = bit_to_lut.find(sig_R);
|
||||
if (it_R != bit_to_lut.end())
|
||||
lut_r = it_R->second.first;
|
||||
if (sig_R.wire) {
|
||||
// Merge R LUT and D LUT into one. If it cannot be done, try to at least merge CE/S.
|
||||
if (!merge_lut(lut_d_post_r, lut_d_post_s, lut_r, inv_r, SigBit(State::S0), max_lut_size))
|
||||
goto unmap;
|
||||
// If this gets rid of an S LUT, it's worth it.
|
||||
if (it_R != bit_to_lut.end())
|
||||
worthy_post_r = true;
|
||||
} else if (sig_R.data != (inv_r ? State::S1 : State::S0)) {
|
||||
// Strange. Should not happen in a reasonable flow, so bail.
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
unmap:
|
||||
LutData final_lut;
|
||||
if (worthy_post_r) {
|
||||
final_lut = lut_d_post_r;
|
||||
log(" Merging R LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
|
||||
} else if (worthy_post_s) {
|
||||
final_lut = lut_d_post_s;
|
||||
log(" Merging S LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
|
||||
} else if (worthy_post_ce) {
|
||||
final_lut = lut_d_post_ce;
|
||||
log(" Merging CE LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
|
||||
} else {
|
||||
// Nothing to do here.
|
||||
continue;
|
||||
}
|
||||
|
||||
// Okay, we're doing it. Unmap ports.
|
||||
if (worthy_post_r) {
|
||||
cell->unsetParam(ID(IS_R_INVERTED));
|
||||
cell->setPort(ID(R), Const(0, 1));
|
||||
}
|
||||
if (has_s && (worthy_post_r || worthy_post_s)) {
|
||||
cell->unsetParam(ID(IS_S_INVERTED));
|
||||
cell->setPort(ID(S), Const(0, 1));
|
||||
}
|
||||
cell->setPort(ID(CE), Const(1, 1));
|
||||
cell->unsetParam(ID(IS_D_INVERTED));
|
||||
|
||||
// Create the new LUT.
|
||||
Cell *lut_cell = 0;
|
||||
switch (GetSize(final_lut.second)) {
|
||||
case 1:
|
||||
lut_cell = module->addCell(NEW_ID, ID(LUT1));
|
||||
break;
|
||||
case 2:
|
||||
lut_cell = module->addCell(NEW_ID, ID(LUT2));
|
||||
break;
|
||||
case 3:
|
||||
lut_cell = module->addCell(NEW_ID, ID(LUT3));
|
||||
break;
|
||||
case 4:
|
||||
lut_cell = module->addCell(NEW_ID, ID(LUT4));
|
||||
break;
|
||||
case 5:
|
||||
lut_cell = module->addCell(NEW_ID, ID(LUT5));
|
||||
break;
|
||||
case 6:
|
||||
lut_cell = module->addCell(NEW_ID, ID(LUT6));
|
||||
break;
|
||||
default:
|
||||
log_assert(!"unknown lut size");
|
||||
}
|
||||
lut_cell->attributes = cell_d->attributes;
|
||||
Wire *lut_out = module->addWire(NEW_ID);
|
||||
lut_cell->setParam(ID(INIT), final_lut.first);
|
||||
cell->setPort(ID(D), lut_out);
|
||||
lut_cell->setPort(ID(O), lut_out);
|
||||
lut_cell->setPort(ID(I0), final_lut.second[0]);
|
||||
if (GetSize(final_lut.second) >= 2)
|
||||
lut_cell->setPort(ID(I1), final_lut.second[1]);
|
||||
if (GetSize(final_lut.second) >= 3)
|
||||
lut_cell->setPort(ID(I2), final_lut.second[2]);
|
||||
if (GetSize(final_lut.second) >= 4)
|
||||
lut_cell->setPort(ID(I3), final_lut.second[3]);
|
||||
if (GetSize(final_lut.second) >= 5)
|
||||
lut_cell->setPort(ID(I4), final_lut.second[4]);
|
||||
if (GetSize(final_lut.second) >= 6)
|
||||
lut_cell->setPort(ID(I5), final_lut.second[5]);
|
||||
}
|
||||
}
|
||||
}
|
||||
} XilinxDffOptPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
||||
|
|
@ -14,6 +14,6 @@ select -assert-count 1 t:BUFG
|
|||
select -assert-count 4 t:FDRE
|
||||
select -assert-count 1 t:FDSE
|
||||
select -assert-count 1 t:LUT2
|
||||
select -assert-count 2 t:LUT3
|
||||
select -assert-count 4 t:LUT5
|
||||
select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT3 t:LUT5 %% t:* %D
|
||||
select -assert-count 3 t:LUT5
|
||||
select -assert-count 1 t:LUT6
|
||||
select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D
|
||||
|
|
|
|||
|
|
@ -0,0 +1,216 @@
|
|||
read_verilog << EOT
|
||||
|
||||
// FDRE, mergeable CE and R.
|
||||
|
||||
module t0 (...);
|
||||
input wire clk;
|
||||
input wire [7:0] i;
|
||||
output wire [7:0] o;
|
||||
|
||||
wire [7:0] tmp ;
|
||||
|
||||
LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
|
||||
LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
|
||||
LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2]));
|
||||
|
||||
FDRE ff (.D(tmp[0]), .CE(tmp[1]), .R(tmp[2]), .Q(o[0]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDRE
|
||||
select -assert-count 1 t:LUT6
|
||||
select -assert-count 3 t:LUT2
|
||||
select -assert-none t:FDRE t:LUT6 t:LUT2 %% t:* %D
|
||||
|
||||
design -load t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDRE
|
||||
select -assert-count 1 t:LUT4
|
||||
select -assert-count 3 t:LUT2
|
||||
select -assert-none t:FDRE t:LUT4 t:LUT2 %% t:* %D
|
||||
|
||||
design -reset
|
||||
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
// FDSE, mergeable CE and S, inversions.
|
||||
|
||||
module t0 (...);
|
||||
input wire clk;
|
||||
input wire [7:0] i;
|
||||
output wire [7:0] o;
|
||||
|
||||
wire [7:0] tmp ;
|
||||
|
||||
LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
|
||||
LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
|
||||
LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2]));
|
||||
|
||||
FDSE #(.IS_D_INVERTED(1'b1), .IS_S_INVERTED(1'b1)) ff (.D(tmp[0]), .CE(tmp[1]), .S(tmp[2]), .Q(o[0]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDSE
|
||||
select -assert-count 1 t:LUT6
|
||||
select -assert-count 3 t:LUT2
|
||||
select -assert-none t:FDSE t:LUT6 t:LUT2 %% t:* %D
|
||||
|
||||
design -load t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDSE
|
||||
select -assert-count 1 t:LUT4
|
||||
select -assert-count 3 t:LUT2
|
||||
select -assert-none t:FDSE t:LUT4 t:LUT2 %% t:* %D
|
||||
|
||||
design -reset
|
||||
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
// FDCE, mergeable CE.
|
||||
|
||||
module t0 (...);
|
||||
input wire clk;
|
||||
input wire [7:0] i;
|
||||
output wire [7:0] o;
|
||||
|
||||
wire [7:0] tmp ;
|
||||
|
||||
LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
|
||||
LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
|
||||
LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2]));
|
||||
|
||||
FDCE ff (.D(tmp[0]), .CE(tmp[1]), .CLR(tmp[2]), .Q(o[0]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save t0
|
||||
|
||||
equiv_opt -async2sync -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDCE
|
||||
select -assert-count 1 t:LUT4
|
||||
select -assert-count 3 t:LUT2
|
||||
select -assert-none t:FDCE t:LUT4 t:LUT2 %% t:* %D
|
||||
|
||||
design -reset
|
||||
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
// FDSE, mergeable CE and S, but CE only not worth it.
|
||||
|
||||
module t0 (...);
|
||||
input wire clk;
|
||||
input wire [7:0] i;
|
||||
output wire [7:0] o;
|
||||
|
||||
wire [7:0] tmp ;
|
||||
|
||||
LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
|
||||
LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
|
||||
|
||||
FDSE ff (.D(tmp[0]), .CE(i[7]), .S(tmp[1]), .Q(o[0]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDSE
|
||||
select -assert-count 1 t:LUT5
|
||||
select -assert-count 2 t:LUT2
|
||||
select -assert-none t:FDSE t:LUT5 t:LUT2 %% t:* %D
|
||||
|
||||
design -load t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDSE
|
||||
select -assert-count 2 t:LUT2
|
||||
select -assert-none t:FDSE t:LUT2 %% t:* %D
|
||||
|
||||
design -reset
|
||||
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
// FDRSE, mergeable CE, S, R.
|
||||
|
||||
module t0 (...);
|
||||
input wire clk;
|
||||
input wire [7:0] i;
|
||||
output wire [7:0] o;
|
||||
|
||||
wire [7:0] tmp ;
|
||||
|
||||
LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
|
||||
LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
|
||||
LUT2 #(.INIT(4'h8)) lut2 (.I0(i[2]), .I1(i[0]), .O(tmp[2]));
|
||||
LUT2 #(.INIT(4'h6)) lut3 (.I0(i[3]), .I1(i[4]), .O(tmp[3]));
|
||||
|
||||
FDRSE ff (.D(tmp[0]), .CE(tmp[1]), .S(tmp[2]), .R(tmp[3]), .Q(o[0]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDRSE
|
||||
select -assert-count 1 t:LUT6
|
||||
select -assert-count 4 t:LUT2
|
||||
select -assert-none t:FDRSE t:LUT6 t:LUT2 %% t:* %D
|
||||
|
||||
design -load t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDRSE
|
||||
select -assert-count 1 t:LUT4
|
||||
select -assert-count 4 t:LUT2
|
||||
select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D
|
||||
|
||||
design -reset
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
lut0
|
||||
lut1
|
||||
lut2
|
||||
lut3
|
||||
ff
|
||||
ff.D
|
||||
ff.R
|
||||
ff.S
|
||||
ff.CE
|
||||
ff.d
|
||||
ff.r
|
||||
ff.s
|
||||
ff.ce
|
||||
Loading…
Reference in New Issue