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Merge pull request #2149 from whitequark/cxxrtl-unbuffer-outputs 

cxxrtl: unbuffer output wires of toplevel module
This commit is contained in:
whitequark 2020-06-12 01:59:35 +00:00 committed by GitHub
parent 8b4eb78849 d5ecd4a570
commit a1785e988b
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 24 additions and 20 deletions
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38
backends/cxxrtl/cxxrtl_backend.cc
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@ -171,11 +171,6 @@ struct Scheduler {
} }
}; };
bool is_input_wire(const RTLIL::Wire *wire)
{
return wire->port_input && !wire->port_output;
}
bool is_unary_cell(RTLIL::IdString type) bool is_unary_cell(RTLIL::IdString type)
{ {
return type.in( return type.in(
@ -804,7 +799,7 @@ struct CxxrtlWorker {
default: default:
log_assert(false); log_assert(false);
} }
} else if (unbuffered_wires[chunk.wire] || is_input_wire(chunk.wire)) { } else if (unbuffered_wires[chunk.wire]) {
f << mangle(chunk.wire); f << mangle(chunk.wire);
} else { } else {
f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr"); f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
@ -1440,12 +1435,11 @@ struct CxxrtlWorker {
if (elided_wires.count(wire)) if (elided_wires.count(wire))
return; return;
if (unbuffered_wires[wire]) { if (localized_wires[wire] && is_local_context) {
if (localized_wires[wire] == is_local_context) {
dump_attrs(wire); dump_attrs(wire);
f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n"; f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
} }
} else if (!is_local_context) { if (!localized_wires[wire] && !is_local_context) {
std::string width; std::string width;
if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) { if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) {
width = wire->get_string_attribute(ID(cxxrtl_width)); width = wire->get_string_attribute(ID(cxxrtl_width));
@ -1454,14 +1448,21 @@ struct CxxrtlWorker {
} }
dump_attrs(wire); dump_attrs(wire);
f << indent << (is_input_wire(wire) ? "value" : "wire") << "<" << width << "> " << mangle(wire); f << indent;
if (wire->port_input && wire->port_output)
f << "/*inout*/ ";
else if (wire->port_input)
f << "/*input*/ ";
else if (wire->port_output)
f << "/*output*/ ";
f << (unbuffered_wires[wire] ? "value" : "wire") << "<" << width << "> " << mangle(wire);
if (wire->has_attribute(ID::init)) { if (wire->has_attribute(ID::init)) {
f << " "; f << " ";
dump_const_init(wire->attributes.at(ID::init)); dump_const_init(wire->attributes.at(ID::init));
} }
f << ";\n"; f << ";\n";
if (edge_wires[wire]) { if (edge_wires[wire]) {
if (is_input_wire(wire)) { if (unbuffered_wires[wire]) {
f << indent << "value<" << width << "> prev_" << mangle(wire); f << indent << "value<" << width << "> prev_" << mangle(wire);
if (wire->has_attribute(ID::init)) { if (wire->has_attribute(ID::init)) {
f << " "; f << " ";
@ -1472,7 +1473,7 @@ struct CxxrtlWorker {
for (auto edge_type : edge_types) { for (auto edge_type : edge_types) {
if (edge_type.first.wire == wire) { if (edge_type.first.wire == wire) {
std::string prev, next; std::string prev, next;
if (is_input_wire(wire)) { if (unbuffered_wires[wire]) {
prev = "prev_" + mangle(edge_type.first.wire); prev = "prev_" + mangle(edge_type.first.wire);
next = mangle(edge_type.first.wire); next = mangle(edge_type.first.wire);
} else { } else {
@ -1595,9 +1596,9 @@ struct CxxrtlWorker {
inc_indent(); inc_indent();
f << indent << "bool changed = false;\n"; f << indent << "bool changed = false;\n";
for (auto wire : module->wires()) { for (auto wire : module->wires()) {
if (elided_wires.count(wire) || unbuffered_wires.count(wire)) if (elided_wires.count(wire))
continue; continue;
if (is_input_wire(wire)) { if (unbuffered_wires[wire]) {
if (edge_wires[wire]) if (edge_wires[wire])
f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n"; f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n";
continue; continue;
@ -1970,6 +1971,8 @@ struct CxxrtlWorker {
if (module->get_bool_attribute(ID(cxxrtl_blackbox))) { if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
for (auto port : module->ports) { for (auto port : module->ports) {
RTLIL::Wire *wire = module->wire(port); RTLIL::Wire *wire = module->wire(port);
if (wire->port_input && !wire->port_output)
unbuffered_wires.insert(wire);
if (wire->has_attribute(ID(cxxrtl_edge))) { if (wire->has_attribute(ID(cxxrtl_edge))) {
RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl_edge)]; RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl_edge)];
if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire)) if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire))
@ -2158,13 +2161,14 @@ struct CxxrtlWorker {
for (auto wire : module->wires()) { for (auto wire : module->wires()) {
if (feedback_wires[wire]) continue; if (feedback_wires[wire]) continue;
if (wire->port_id != 0) continue; if (wire->port_output && !module->get_bool_attribute(ID::top)) continue;
if (wire->get_bool_attribute(ID::keep)) continue;
if (wire->name.begins_with("$") && !unbuffer_internal) continue; if (wire->name.begins_with("$") && !unbuffer_internal) continue;
if (wire->name.begins_with("\\") && !unbuffer_public) continue; if (wire->name.begins_with("\\") && !unbuffer_public) continue;
if (edge_wires[wire]) continue;
if (flow.wire_sync_defs.count(wire) > 0) continue; if (flow.wire_sync_defs.count(wire) > 0) continue;
unbuffered_wires.insert(wire); unbuffered_wires.insert(wire);
if (edge_wires[wire]) continue;
if (wire->get_bool_attribute(ID::keep)) continue;
if (wire->port_input || wire->port_output) continue;
if (wire->name.begins_with("$") && !localize_internal) continue; if (wire->name.begins_with("$") && !localize_internal) continue;
if (wire->name.begins_with("\\") && !localize_public) continue; if (wire->name.begins_with("\\") && !localize_public) continue;
localized_wires.insert(wire); localized_wires.insert(wire);