mirror of https://github.com/YosysHQ/yosys.git
check: Also check for conflicts with constant drivers
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f9257d3192
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@ -112,11 +112,10 @@ struct CheckPass : public Pass {
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for (size_t i = 0; i < all_cases.size(); i++) {
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for (auto action : all_cases[i]->actions) {
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for (auto bit : sigmap(action.first))
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if (bit.wire) {
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wire_drivers[bit].push_back(
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stringf("action %s <= %s (case rule) in process %s",
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log_signal(action.first), log_signal(action.second), log_id(proc_it.first)));
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}
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for (auto bit : sigmap(action.second))
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if (bit.wire) used_wires.insert(bit);
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}
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@ -134,7 +133,6 @@ struct CheckPass : public Pass {
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if (bit.wire) used_wires.insert(bit);
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for (auto action : sync->actions) {
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for (auto bit : sigmap(action.first))
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if (bit.wire)
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wire_drivers[bit].push_back(
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stringf("action %s <= %s (sync rule) in process %s",
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log_signal(action.first), log_signal(action.second), log_id(proc_it.first)));
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@ -176,7 +174,8 @@ struct CheckPass : public Pass {
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if (logic_cell)
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topo.edge(stringf("cell %s (%s)", log_id(cell), log_id(cell->type)),
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stringf("wire %s", log_signal(sig[i])));
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if (sig[i].wire)
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if (sig[i].wire || !cell->input(conn.first))
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wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)",
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log_id(conn.first), i, log_id(cell), log_id(cell->type)));
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}
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@ -192,6 +191,7 @@ struct CheckPass : public Pass {
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if (wire->port_input) {
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SigSpec sig = sigmap(wire);
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for (int i = 0; i < GetSize(sig); i++)
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if (sig[i].wire || !wire->port_output)
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wire_drivers[sig[i]].push_back(stringf("module input %s[%d]", log_id(wire), i));
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}
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if (wire->port_output)
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@ -212,6 +212,15 @@ struct CheckPass : public Pass {
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}
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}
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for (auto state : {State::S0, State::S1, State::Sx})
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if (wire_drivers.count(state)) {
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string message = stringf("Drivers conflicting with a constant %s driver:\n", log_signal(state));
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for (auto str : wire_drivers[state])
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message += stringf(" %s\n", str.c_str());
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log_warning("%s", message.c_str());
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counter++;
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}
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for (auto it : wire_drivers)
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if (wire_drivers_count[it.first] > 1) {
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string message = stringf("multiple conflicting drivers for %s.%s:\n", log_id(module), log_signal(it.first));
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@ -0,0 +1,51 @@
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read_verilog <<EOT
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module top(input A, output Y);
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assign A = 1;
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assign Y = A;
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endmodule
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EOT
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hierarchy -top top; proc
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logger -expect warning "Drivers conflicting with a constant" 1
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logger -expect log "Found and reported 1 problems." 1
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check
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logger -check-expected
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design -reset
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read_verilog <<EOT
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module top(input A, output Y);
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buffer some_buffer(A, Y);
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assign Y = 1;
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endmodule
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module buffer(input A, output Y);
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assign Y = A;
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endmodule
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EOT
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hierarchy -top top; proc
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logger -expect warning "Drivers conflicting with a constant" 1
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logger -expect log "Found and reported 1 problems." 1
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check
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logger -check-expected
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design -reset
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read_verilog <<EOT
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module top(input clk, input A, output Y);
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reg Q;
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always @(posedge clk) Q <= A;
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assign Q = 1;
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assign Y = A;
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endmodule
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EOT
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hierarchy -top top
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logger -expect warning "Drivers conflicting with a constant" 1
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logger -expect log "Found and reported 1 problems." 1
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check
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logger -check-expected
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