mirror of https://github.com/YosysHQ/yosys.git
synth_xilinx -dff to work with abc too
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@ -108,10 +108,11 @@ struct SynthXilinxPass : public ScriptPass
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log(" flatten design before synthesis\n");
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log("\n");
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log(" -dff\n");
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log(" run 'abc9' with -dff option\n");
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log(" run 'abc'/'abc9' with -dff option\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with '-dff -D 1' options\n");
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log(" run 'abc' with '-D 1' option to enable flip-flop retiming.\n");
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log(" implies -dff.\n");
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log("\n");
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log(" -abc9\n");
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log(" use new ABC9 flow (EXPERIMENTAL)\n");
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@ -195,6 +196,7 @@ struct SynthXilinxPass : public ScriptPass
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continue;
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}
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if (args[argidx] == "-retime") {
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dff_mode = true;
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retime = true;
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continue;
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}
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@ -542,7 +544,7 @@ struct SynthXilinxPass : public ScriptPass
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if (flatten_before_abc)
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run("flatten");
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if (help_mode)
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run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
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run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for 'nowidelut', '-dff', '-retime')");
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else if (abc9) {
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if (family != "xc7")
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log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
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@ -565,10 +567,16 @@ struct SynthXilinxPass : public ScriptPass
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run("techmap -map +/xilinx/abc9_unmap.v");
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}
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else {
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std::string abc_opts;
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if (nowidelut)
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run("abc -luts 2:2,3,6:5" + string(retime ? " -dff -D 1" : ""));
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abc_opts += " -luts 2:2,3,6:5";
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else
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run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff -D 1" : ""));
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abc_opts += " -luts 2:2,3,6:5,10,20";
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if (dff_mode)
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abc_opts += " -dff";
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if (retime)
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abc_opts += " -D 1";
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run("abc" + abc_opts);
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}
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run("clean");
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@ -581,7 +589,7 @@ struct SynthXilinxPass : public ScriptPass
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techmap_args += stringf("[-map %s]", ff_map_file.c_str());
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else if (!abc9)
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techmap_args += stringf(" -map %s", ff_map_file.c_str());
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run("techmap " + techmap_args, "(option without '-abc9')");
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run("techmap " + techmap_args, "(only if '-abc9')");
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run("xilinx_dffopt");
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}
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