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Merge pull request #4625 from povik/cellmatch-lut 

cellmatch: Size the `lut` attribute
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Martin Povišer 2024-10-11 14:08:55 +02:00 committed by GitHub
parent 0200a7680a ec42b42bd9
commit a00137c2f6
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1 changed files with 1 additions and 1 deletions
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passes/techmap/cellmatch.cc
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@ -223,7 +223,7 @@ struct CellmatchPass : Pass {
for (auto bit : outputs) {
log_assert(bit.is_wire());
bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]);
bit.wire->attributes[ID(lut)] = luts[no++];
bit.wire->attributes[ID(lut)] = Const(luts[no++], 1 << inputs.size());
}
}