From ec42b42bd93d08839a0f6315b807042990f093e6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 2 Oct 2024 11:26:15 +0200
Subject: [PATCH] cellmatch: Size the `lut` attribute

---
 passes/techmap/cellmatch.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc
index a21a4fbad..235599972 100644
--- a/passes/techmap/cellmatch.cc
+++ b/passes/techmap/cellmatch.cc
@@ -223,7 +223,7 @@ struct CellmatchPass : Pass {
 				for (auto bit : outputs) {
 					log_assert(bit.is_wire());
 					bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]);
-					bit.wire->attributes[ID(lut)] = luts[no++];
+					bit.wire->attributes[ID(lut)] = Const(luts[no++], 1 << inputs.size());
 				}
 			}