mirror of https://github.com/YosysHQ/yosys.git
Changed LEVEL resets to be edge triggered anyway
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@ -86,7 +86,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
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end
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"LEVEL": begin
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always @(posedge CLK or RST) begin
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always @(posedge CLK or posedge RST) begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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@ -204,7 +204,7 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
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end
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"LEVEL": begin
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always @(posedge CLK or RST) begin
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always @(posedge CLK or posedge RST) begin
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//Main counter
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if(KEEP) begin
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@ -339,7 +339,7 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
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end
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"LEVEL": begin
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always @(posedge CLK or RST) begin
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always @(posedge CLK or posedge RST) begin
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//Main counter
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if(KEEP) begin
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@ -439,7 +439,7 @@ module GP_COUNT8(
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end
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"LEVEL": begin
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always @(posedge CLK or RST) begin
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always @(posedge CLK or posedge RST) begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_TO;
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