riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Docs: Note on debug for memory_libmap

This commit is contained in:
Krystine Sherwin 2024-02-05 15:38:01 +13:00
parent fae35fe98b
commit 9eed04dd4b
No known key found for this signature in database
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
docs/source/using_yosys/synthesis/memory.rst
View File

@ -83,6 +83,13 @@ my_memory_map.v` then uses :cmd:ref:`techmap` to map to hardware primitives. Any
leftover memory cells unable to be converted are then picked up by
:cmd:ref:`memory_map` and mapped to DFFs and address decoders.
.. note::
More information about what mapping options are available and associated
costs of each can be found by enabling debug outputs. This can be done with
the :cmd:ref:`debug` command, or by using the ``-g`` flag when calling Yosys
to globally enable debug messages.
For more on the lib format for :cmd:ref:`memory_libmap`, see
`passes/memory/memlib.md
<https://github.com/YosysHQ/yosys/blob/master/passes/memory/memlib.md>`_