mirror of https://github.com/YosysHQ/yosys.git
hierarchy: Ignore width mismatch from verific
But only if it's also a blackbox module with parameters (i.e. it *could* be parametrizable width).
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9e9213c011
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@ -978,6 +978,11 @@ struct HierarchyPass : public Pass {
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}
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}
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}
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}
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bool verific_mod = false;
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#ifdef YOSYS_ENABLE_VERIFIC
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verific_mod = verific_import_pending;
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#endif
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if (top_mod == nullptr && !load_top_mod.empty()) {
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if (top_mod == nullptr && !load_top_mod.empty()) {
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#ifdef YOSYS_ENABLE_VERIFIC
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#ifdef YOSYS_ENABLE_VERIFIC
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if (verific_import_pending) {
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if (verific_import_pending) {
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@ -1418,13 +1423,18 @@ struct HierarchyPass : public Pass {
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if (m == nullptr)
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if (m == nullptr)
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continue;
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continue;
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if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) {
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bool boxed_params = false;
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IdString new_m_name = m->derive(design, cell->parameters, true);
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if (m->get_blackbox_attribute() && !cell->parameters.empty()) {
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if (new_m_name.empty())
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if (m->get_bool_attribute(ID::dynports)) {
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continue;
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IdString new_m_name = m->derive(design, cell->parameters, true);
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if (new_m_name != m->name) {
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if (new_m_name.empty())
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m = design->module(new_m_name);
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continue;
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blackbox_derivatives.insert(m);
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if (new_m_name != m->name) {
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m = design->module(new_m_name);
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blackbox_derivatives.insert(m);
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}
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} else {
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boxed_params = true;
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}
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}
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}
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}
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@ -1440,8 +1450,12 @@ struct HierarchyPass : public Pass {
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SigSpec sig = conn.second;
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SigSpec sig = conn.second;
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if (!keep_portwidths && GetSize(w) != GetSize(conn.second))
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bool resize_widths = !keep_portwidths && GetSize(w) != GetSize(conn.second);
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{
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if (resize_widths && verific_mod && boxed_params)
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log_warning("Ignoring width mismatch on %s.%s.%s from verific, is port width parametrizable?\n",
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log_id(module), log_id(cell), log_id(conn.first)
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);
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else if (resize_widths) {
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if (GetSize(w) < GetSize(conn.second))
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if (GetSize(w) < GetSize(conn.second))
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{
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{
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int n = GetSize(conn.second) - GetSize(w);
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int n = GetSize(conn.second) - GetSize(w);
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