mirror of https://github.com/YosysHQ/yosys.git
Disabled broken $mem support in verilog backend
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@ -790,7 +790,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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return true;
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}
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if (cell->type == "$mem")
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if (cell->type == "$mem" && false) // FIXME!
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{
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RTLIL::IdString memid = cell->parameters["\\MEMID"].decode_string();
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std::string mem_id = id(cell->parameters["\\MEMID"].decode_string());
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