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Add tests/various/abc9.{v,ys} with SCC test

This commit is contained in:
Eddie Hung 2019-06-24 21:52:53 -07:00
parent cec2292b0b
commit 9dca024a30
2 changed files with 19 additions and 0 deletions
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5
tests/various/abc9.v Normal file
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module abc9_test027(output reg o);
initial o = 1'b0;
always @*
o <= ~o;
endmodule

14
tests/various/abc9.ys Normal file
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read_verilog abc9.v
proc
design -save gold
abc9 -lut 4
check
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter