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Further clean up `passes/cmds/select.cc`. 

Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
This commit is contained in:
Alberto Gonzalez 2020-03-16 20:32:46 +00:00
parent 70093698f5
commit 9d9bbdce5d
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GPG Key ID: 8395A8BA109708B2
2 changed files with 9 additions and 12 deletions
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1
kernel/rtlil.h
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@ -560,7 +560,6 @@ namespace RTLIL
ObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { } ObjRange(decltype(list_p) list_p, int *refcount_p) : list_p(list_p), refcount_p(refcount_p) { }
RTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); } RTLIL::ObjIterator<T> begin() { return RTLIL::ObjIterator<T>(list_p, refcount_p); }
RTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); } RTLIL::ObjIterator<T> end() { return RTLIL::ObjIterator<T>(); }
bool contains(const RTLIL::IdString &what) { return (list_p->count(what) > 0); }
size_t size() const { size_t size() const {
return list_p->size(); return list_p->size();

20
passes/cmds/select.cc
View File

@ -228,7 +228,7 @@ static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs)
{ {
for (auto cell : mod->cells()) for (auto cell : mod->cells())
{ {
if (!design->has(cell->type)) if (design->module(cell->type) == nullptr)
continue; continue;
lhs.selected_modules.insert(cell->type); lhs.selected_modules.insert(cell->type);
} }
@ -242,7 +242,7 @@ static void select_op_cells_to_modules(RTLIL::Design *design, RTLIL::Selection &
for (auto mod : design->modules()) for (auto mod : design->modules())
if (lhs.selected_module(mod->name)) if (lhs.selected_module(mod->name))
for (auto cell : mod->cells()) for (auto cell : mod->cells())
if (lhs.selected_member(mod->name, cell->name) && design->has(cell->type)) if (lhs.selected_member(mod->name, cell->name) && (design->module(cell->type) != nullptr))
new_sel.selected_modules.insert(cell->type); new_sel.selected_modules.insert(cell->type);
lhs = new_sel; lhs = new_sel;
} }
@ -252,7 +252,7 @@ static void select_op_module_to_cells(RTLIL::Design *design, RTLIL::Selection &l
RTLIL::Selection new_sel(false); RTLIL::Selection new_sel(false);
for (auto mod : design->modules()) for (auto mod : design->modules())
for (auto cell : mod->cells()) for (auto cell : mod->cells())
if (design->has(cell->type) && lhs.selected_whole_module(cell->type)) if ((design->module(cell->type) != nullptr) && lhs.selected_whole_module(cell->type))
new_sel.selected_members[mod->name].insert(cell->name); new_sel.selected_members[mod->name].insert(cell->name);
lhs = new_sel; lhs = new_sel;
} }
@ -333,7 +333,7 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R
for (auto &it : rhs.selected_members) for (auto &it : rhs.selected_members)
{ {
if (!design->has(it.first)) if (design->module(it.first) == nullptr)
continue; continue;
RTLIL::Module *mod = design->module(it.first); RTLIL::Module *mod = design->module(it.first);
@ -1264,7 +1264,7 @@ struct SelectPass : public Pass {
} }
if (arg == "-module" && argidx+1 < args.size()) { if (arg == "-module" && argidx+1 < args.size()) {
RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]); RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
if (!design->has(mod_name)) if (design->module(mod_name) == nullptr)
log_cmd_error("No such module: %s\n", id2cstr(mod_name)); log_cmd_error("No such module: %s\n", id2cstr(mod_name));
design->selected_active_module = mod_name.str(); design->selected_active_module = mod_name.str();
got_module = true; got_module = true;
@ -1578,15 +1578,13 @@ struct CdPass : public Pass {
std::string modname = RTLIL::escape_id(args[1]); std::string modname = RTLIL::escape_id(args[1]);
if (!design->has(modname) == 0 && !design->selected_active_module.empty()) { if (design->module(modname) == nullptr && !design->selected_active_module.empty()) {
RTLIL::Module *module = nullptr; RTLIL::Module *module = design->module(design->selected_active_module);
if (design->has(design->selected_active_module) > 0) if (module != nullptr && module->cell(modname) != nullptr)
module = design->module(design->selected_active_module);
if (module != nullptr && module->cells().contains(modname))
modname = module->cell(modname)->type.str(); modname = module->cell(modname)->type.str();
} }
if (design->has(modname)) { if (design->module(modname) != nullptr) {
design->selected_active_module = modname; design->selected_active_module = modname;
design->selection_stack.back() = RTLIL::Selection(); design->selection_stack.back() = RTLIL::Selection();
select_filter_active_mod(design, design->selection_stack.back()); select_filter_active_mod(design, design->selection_stack.back());