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Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-02-26 15:02:03 +01:00
parent d1cb5150aa
commit 9cd9f5fc78
1 changed files with 25 additions and 0 deletions
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25
frontends/verific/verific.cc
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@ -544,6 +544,31 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
return true; return true;
} }
if (inst->Type() == OPER_NTO1MUX) {
module->addShr(inst_name, IN2, IN1, net_map_at(inst->GetOutput()));
return true;
}
if (inst->Type() == OPER_WIDE_NTO1MUX)
{
SigSpec data = IN2, out = OUT;
int wordsize_bits = ceil_log2(GetSize(out));
int wordsize = 1 << wordsize_bits;
SigSpec sel = {IN1, SigSpec(State::S0, wordsize_bits)};
SigSpec padded_data;
for (int i = 0; i < GetSize(data); i += GetSize(out)) {
SigSpec d = data.extract(i, GetSize(out));
d.extend_u0(wordsize);
padded_data.append(d);
}
module->addShr(inst_name, padded_data, sel, out);
return true;
}
if (inst->Type() == OPER_WIDE_TRI) { if (inst->Type() == OPER_WIDE_TRI) {
module->addMux(inst_name, RTLIL::SigSpec(RTLIL::State::Sz, inst->OutputSize()), IN, net_map_at(inst->GetControl()), OUT); module->addMux(inst_name, RTLIL::SigSpec(RTLIL::State::Sz, inst->OutputSize()), IN, net_map_at(inst->GetControl()), OUT);
return true; return true;