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opt_merge: Remove and reinsert init when connecting nets. 

Mutating the SigMap by adding a new connection will throw off FfInitVals
index.  Work around this by removing the relevant init values from index
whenever we connect nets, then re-add the new init value.

Should fix #2920.
This commit is contained in:
Marcelina Kościelnicka 2021-08-22 17:01:58 +02:00
parent 62d41d4639
commit 9cbff3a4a9
1 changed files with 4 additions and 3 deletions
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7
passes/opt/opt_merge.cc
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@ -282,11 +282,12 @@ struct OptMergeWorker
RTLIL::SigSpec other_sig = r.first->second->getPort(it.first); RTLIL::SigSpec other_sig = r.first->second->getPort(it.first);
log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(), log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
log_signal(it.second), log_signal(other_sig)); log_signal(it.second), log_signal(other_sig));
Const init = initvals(other_sig);
initvals.remove_init(it.second);
initvals.remove_init(other_sig);
module->connect(RTLIL::SigSig(it.second, other_sig)); module->connect(RTLIL::SigSig(it.second, other_sig));
assign_map.add(it.second, other_sig); assign_map.add(it.second, other_sig);
initvals.set_init(other_sig, init);
if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell->type))
initvals.remove_init(it.second);
} }
} }
log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());