mirror of https://github.com/YosysHQ/yosys.git
sv: Improve tests
Signed-off-by: David Shah <dave@ds0.me>
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typedef logic [3:0] outer_uint4_t;
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module top;
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outer_uint4_t u4_i = 8'hA5;
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always @(*) assert(u4_i == 4'h5);
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typedef logic [3:0] inner_type;
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inner_type inner_i1 = 8'h5A;
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always @(*) assert(inner_i1 == 4'hA);
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if (1) begin: genblock
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typedef logic [7:0] inner_type;
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inner_type inner_gb_i = 8'hA5;
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always @(*) assert(inner_gb_i == 8'hA5);
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end
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inner_type inner_i2 = 8'h42;
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always @(*) assert(inner_i2 == 4'h2);
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endmodule
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