riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix 5bba9c3, closes #1876 

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
This commit is contained in:
Claire Wolf 2020-04-14 21:05:07 +02:00
parent 7a36728b2f
commit 9b4dab397e
1 changed files with 13 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
frontends/ast/genrtlil.cc
View File

@ -1326,20 +1326,25 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
{ {
if (width_hint < 0) if (width_hint < 0)
detectSignWidth(width_hint, sign_hint); detectSignWidth(width_hint, sign_hint);
is_signed = sign_hint;
RTLIL::SigSpec cond = children[0]->genRTLIL(); RTLIL::SigSpec cond = children[0]->genRTLIL();
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (cond.is_fully_const()) {
if (cond.is_fully_def())
{
if (cond.as_bool()) { if (cond.as_bool()) {
sig = children[1]->genRTLIL(width_hint, sign_hint); sig = children[1]->genRTLIL(width_hint, sign_hint);
widthExtend(this, sig, sig.size(), children[1]->is_signed); log_assert(is_signed == children[1]->is_signed);
} } else {
else {
sig = children[2]->genRTLIL(width_hint, sign_hint); sig = children[2]->genRTLIL(width_hint, sign_hint);
widthExtend(this, sig, sig.size(), children[2]->is_signed); log_assert(is_signed == children[2]->is_signed);
} }
widthExtend(this, sig, sig.size(), is_signed);
} }
else { else
{
RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint); RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint); RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
@ -1347,7 +1352,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false); cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false);
int width = max(val1.size(), val2.size()); int width = max(val1.size(), val2.size());
is_signed = children[1]->is_signed && children[2]->is_signed; log_assert(is_signed == children[1]->is_signed);
log_assert(is_signed == children[2]->is_signed);
widthExtend(this, val1, width, is_signed); widthExtend(this, val1, width, is_signed);
widthExtend(this, val2, width, is_signed); widthExtend(this, val2, width, is_signed);