Merge pull request #1000 from bwidawsk/synth-format

Add clang format, and use on intel_synth (v2)
This commit is contained in:
Clifford Wolf 2019-05-09 18:41:38 +02:00 committed by GitHub
commit 9b2b0d91d2
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 224 additions and 222 deletions

13
.clang-format Normal file
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@ -0,0 +1,13 @@
# Default Linux style
BasedOnStyle: LLVM
IndentWidth: 8
UseTab: Always
BreakBeforeBraces: Linux
AllowShortIfStatementsOnASingleLine: false
IndentCaseLabels: false
# From CodingReadme
TabWidth: 8
ContinuationIndentWidth: 2
ColumnLimit: 150
# BreakBeforeBraces: Linux

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@ -17,10 +17,10 @@
*
*/
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
#include "kernel/register.h"
#include "kernel/rtlil.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -97,8 +97,7 @@ struct SynthIntelPass : public ScriptPass {
clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-family" && argidx + 1 < args.size()) {
family_opt = args[++argidx];
continue;
@ -145,7 +144,8 @@ struct SynthIntelPass : public ScriptPass {
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
if (family_opt != "max10" && family_opt !="a10gx" && family_opt != "cyclonev" && family_opt !="cycloneiv" && family_opt !="cycloneive" && family_opt != "cyclone10")
if (family_opt != "max10" && family_opt != "a10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" &&
family_opt != "cycloneive" && family_opt != "cyclone10")
log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
log_header(design, "Executing SYNTH_INTEL pass.\n");
@ -158,8 +158,7 @@ struct SynthIntelPass : public ScriptPass {
void script() YS_OVERRIDE
{
if (check_label("begin"))
{
if (check_label("begin")) {
if (check_label("family") && family_opt == "max10")
run("read_verilog -sv -lib +/intel/max10/cells_sim.v");
else if (check_label("family") && family_opt == "a10gx")
@ -178,27 +177,23 @@ struct SynthIntelPass : public ScriptPass {
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
if (flatten && check_label("flatten", "(unless -noflatten)"))
{
if (flatten && check_label("flatten", "(unless -noflatten)")) {
run("proc");
run("flatten");
run("tribuf -logic");
run("deminout");
}
if (check_label("coarse"))
{
if (check_label("coarse")) {
run("synth -run coarse");
}
if (!nobram && check_label("bram", "(skip if -nobram)"))
{
if (!nobram && check_label("bram", "(skip if -nobram)")) {
run("memory_bram -rules +/intel/common/brams.txt");
run("techmap -map +/intel/common/brams_map.v");
}
if (check_label("fine"))
{
if (check_label("fine")) {
run("opt -fast -mux_undef -undriven -fine -full");
run("memory_map");
run("opt -undriven -fine");
@ -213,8 +208,7 @@ struct SynthIntelPass : public ScriptPass {
run("abc -markgroups -dff", "(only if -retime)");
}
if (check_label("map_luts"))
{
if (check_label("map_luts")) {
if (family_opt == "a10gx" || family_opt == "cyclonev")
run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
else
@ -222,8 +216,7 @@ struct SynthIntelPass : public ScriptPass {
run("clean");
}
if (check_label("map_cells"))
{
if (check_label("map_cells")) {
if (!noiopads)
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
if (family_opt == "max10")
@ -242,24 +235,20 @@ struct SynthIntelPass : public ScriptPass {
run("clean -purge");
}
if (check_label("check"))
{
if (check_label("check")) {
run("hierarchy -check");
run("stat");
run("check -noinit");
}
if (check_label("vqm"))
{
if (check_label("vqm")) {
if (!vout_file.empty() || help_mode)
run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s",
help_mode ? "<file-name>" : vout_file.c_str()));
}
if (check_label("vpr"))
{
if (!blif_file.empty() || help_mode)
{
if (check_label("vpr")) {
if (!blif_file.empty() || help_mode) {
run(stringf("opt_clean -purge"));
run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
}